Characterization and Modeling of High Power Microwave Effects in CMOS Microelectronics

The intentional use of high power microwave (HPM) signals to disrupt microelectronic systems is a substantial threat to vital infrastructure. Conventional methods to assess HPM threats involve empirical testing of electronic equipment, which provides no insight into fundamental mechanisms of HPM induced upset. The work presented in this dissertation is part of a broad effort to develop more effective means for HPM threat assessment. Comprehensive experimental evaluation of CMOS digital electronics was performed to provide critical information of the elementary mechanisms that govern the dynamics of HPM effects. Results show that electrostatic discharge (ESD) protection devices play a significant role in the behavior of circuits irradiated by HPM pulses. The PN junctions of the ESD protection devices distort HPM waveforms producing DC voltages at the input of the core logic elements, which produces output bit errors and abnormal circuit power dissipation. The dynamic capacitance of these devices combines with linear parasitic elements to create resonant structures that produce nonlinear circuit dynamics such as spurious oscillations. The insight into the fundamental mechanisms this research has revealed will contribute substantially to the broader effort aimed at identifying and mitigating susceptibilities in critical systems. Also presented in this work is a modeling technique based on scalable analytical circuit models that accounts for the non-quasi-static behavior of the ESD protection PN junctions. The results of circuit simulations employing these device models are in excellent agreement with experimental measurements, and are capable of predicting the threshold of effect for HPM driven non-linear circuit dynamics. For the first time, a deterministic method of evaluating HPM effects based on physical, scalable device parameters has been demonstrated. The modeling presented in this dissertation can be easily integrated into design cycles and will greatly aid the development of electronic systems with improved HPM immunity

Avionics system design for high energy fields: A guide for the designer and airworthiness specialist

Because of the significant differences in transient susceptibility, the use of digital electronics in flight critical systems, and the reduced shielding effects of composite materials, there is a definite need to define pracitices which will minimize electromagnetic susceptibility, to investigate the operational environment, and to develop appropriate testing methods for flight critical systems. The design practices which will lead to reduced electromagnetic susceptibility of avionics systems in high energy fields is described. The levels of emission that can be anticipated from generic digital devices. It is assumed that as data processing equipment becomes an ever larger part of the avionics package, the construction methods of the data processing industry will increasingly carry over into aircraft. In Appendix 1 tentative revisions to RTCA DO-160B, Environmental Conditions and Test Procedures for Airborne Equipment, are presented. These revisions are intended to safeguard flight critical systems from the effects of high energy electromagnetic fields. A very extensive and useful bibliography on both electromagnetic compatibility and avionics issues is included

Diamond power devices: State of the art, modelling and figures of merit

With its remarkable electro-thermal properties such as the highest known thermal conductivity (~22W/cmbold dotK at room temperature) of any material, high hole mobility (> 2000cm2/Vbold dots), high critical electric field (>10MV/cm), and large bandgap (5.47eV), diamond has overwhelming advantages over silicon and other wide bandgap semiconductors (WBG) for ultra-high- voltage and high temperature applications (>3kV and >450 K, respectively). However, despite their tremendous potential, fabricated devices based on this material have not delivered yet the expected high-performance. The main reason behind this is the absence of shallow donor and acceptor species. The second reason is the lack of consistent physical models and design approaches specific to diamond-based devices that could significantly accelerate their development. The third reason is that the best performances of diamond devices are expected only when the highest electric field in reverse bias can be achieved, something that has not been widely obtained yet. In this context, high temperature operation and unique device structures based on the 2DHG formation represent two alternatives which could alleviate the issue of the incomplete ionization of dopant species. Nevertheless, ultra-high temperature operations and device parallelization could result in severe thermal management issues and affect the overall stability and long-term reliability. Additionally, problems connected to the reproducibility and the long-term stability of 2DHG based-devices still need to be resolved. This review paper aims at addressing these issues by providing the power device research community with a detailed set of physical models, device designs and challenges associated to all the aspects of the diamond power device value chain, from the definition of figures of merits, the material growth and processing conditions, to packaging solutions and targeted applications. Finally, the paper will conclude with suggestions on how to design power converters with diamond devices and will provide the roadmap of diamond devices development for power electronics.This work was supported by the U.K. Engineering and Physical Sciences Research Council for the University of Cambridge Centre for Doctoral Training under Grant EP/M506485/1 and by the French ANR Research Agency under grant ANR-16-CE05-0023 #Diamond-HVDC. The research leading to these results has been performed within the GREENDIAMOND project and received funding from the European Community's Horizon 2020 Programme (H2020/2014–2020) under grant agreement no. 640947

Diamond power devices: state of the art, modelling, figures of merit and future perspective

Abstract: With its remarkable electro-thermal properties such as the highest known thermal conductivity (~22 W cm−1∙K−1 at RT of any material, high hole mobility (>2000 cm2 V−1 s−1), high critical electric field (>10 MV cm−1), and large band gap (5.47 eV), diamond has overwhelming advantages over silicon and other wide bandgap semiconductors (WBGs) for ultra-high-voltage and high-temperature (HT) applications (>3 kV and >450 K, respectively). However, despite their tremendous potential, fabricated devices based on this material have not yet delivered the expected high performance. The main reason behind this is the absence of shallow donor and acceptor species. The second reason is the lack of consistent physical models and design approaches specific to diamond-based devices that could significantly accelerate their development. The third reason is that the best performances of diamond devices are expected only when the highest electric field in reverse bias can be achieved, something that has not been widely obtained yet. In this context, HT operation and unique device structures based on the two-dimensional hole gas (2DHG) formation represent two alternatives that could alleviate the issue of the incomplete ionization of dopant species. Nevertheless, ultra-HT operations and device parallelization could result in severe thermal management issues and affect the overall stability and long-term reliability. In addition, problems connected to the reproducibility and long-term stability of 2DHG-based devices still need to be resolved. This review paper aims at addressing these issues by providing the power device research community with a detailed set of physical models, device designs and challenges associated with all the aspects of the diamond power device value chain, from the definition of figures of merit, the material growth and processing conditions, to packaging solutions and targeted applications. Finally, the paper will conclude with suggestions on how to design power converters with diamond devices and will provide the roadmap of diamond device development for power electronics

Development of a fault tolerant MOS field effect power semiconductor switching transistor

This work describes the development of a semiconductor switch to replace an electromechanical contactor as used within the electrical power distribution system of the More Electric Aircraft (MEA; a project begun in the 1990‟s by the United States Air Force). The MEA is safety critical and therefore requires highest reliability components and systems, but subsequent to a short circuit load fault the electro-mechanical contactor switch often welds shut. This risk is increased when using high discharge energy lithium ion dc batteries. Predominately the semiconductor switch controls inductive loads and is required to safely turn off current of up to 10 times the nominal level during sporadic load fault events. The switch requires the lowest static loss (lowest on state resistance), but also the lowest dynamic loss (losses due to the switching event). Presently, unipolar devices provide the lowest dynamic loss, but bipolar devices provide the lowest static loss. One possible solution is use of a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the area of which is sized to suit the fault current, but at relatively high cost in terms of silicon area. The resultant area is typically achieved by several die connected in parallel, unfortunately, such a solution suffers from current share imbalance and the potential of cascade die failure. The use of a parallel combination of unipolar and bipolar device types (MOSFET and Insulated Gate Bipolar Transistors, IGBTs) to form a hybrid appears to offer the potential to reduce the silicon area, and static loss, whilst reducing the impact of the increased dynamic losses of the IGBT. Unfortunately, this goal requires optimised gate timing of the resultant hybrid which proves challenging if the load current is to be shared appropriately during fault switching in order to prevent failure. Some form of single MOS (Metal Oxide Semiconductor) gated integrated hybrid device with self biased bipolar injection is therefore required to ensure highest reliability through a non latching design which offers lowest losses under all conditions and achieves an even temperature distribution. In this work the novel concept of the integrated hybrid device has been investigated at a low Blocking Voltage (BV) rating of 100 V, using computer simulation. The three terminal hybrid silicon DMOS (Double diffused Metal Oxide Semiconductor) device utilises a novel merged Schottky p-type injector to provide self biased entry into a reduced static loss bipolar state in the event of high fault current. The device achieves a specific on state resistance, R(ON,SP) = 1.16 mΩcm2 in bipolar mode (with BV=84 V), that is below the silicon limit line and requires half the area of a traditional unipolar MOSFET to conduct fault current. During comparative standard unclamped inductive switching trials, the hybrid device provides a self clamping action which enables increased inductive energy switching (higher inductance and/or higher load current), relative to that achieved by either the MOSFET or IGBT. The hybrid conducting in bipolar mode switches an inductive load off much faster than that typically achieved by an IGBT (toff =20 ns, in comparison to typically >10 μs for an IGBT). This results in a low turn off energy for the hybrid (1.26*10-4 J/cm2) as compared to that of the IGBT (8.72*10-3 J/cm2). The hybrid dynamic performance is enhanced by the action of the merged Schottky contact which, unlike the IGBT, acts to limit the emitter base voltage (VEB) of the internal PNP Bipolar Junction Transistor, BJT (the integral PNP BJT is otherwise a shared feature with the IGBT). The self biased bipolar activation is achieved at a forward bias (VAK) =1.3 V at temperature (T)= 300 K. The device is latch up free across the operational temperature range of T=233 K to 400 K. A viable charge balanced structure to increase the BV rating to approximately 600 V is also proposed. The resulting performance of the single gated, self biased, hybrid, utilising a novel merged Schottky/P type injector, could lead to a new class of rugged MOS gated power switching devices in silicon and potentially silicon carbide

Concept, design, simulation, and fabrication of an ultra-scalable vertical MOSFET

A new orientation to the conventional MOSFET is proposed. Processing issues, as well as short channel effects have been making planar MOSFET scaling increasingly difficult. It is predicted by the 2001 International Technology Roadmap for Semiconductors (ITRS) that non-planar devices will be needed for production as early as 2007. The device proposed in this thesis is similar in operation to the planar MOSFET, however the current transport from source to drain, normally in the same plane as the wafer surface, is oriented perpendicular to the die surface. The proposed device has successfully been simulated, showing a proof of concept. Fabrication of the proposed devices led to the creation of vertical MOS Gated Tunnel Diodes. This work, in fact, represents possibly the first demonstration of this type of technology. Suggestions are made to improve upon the proposed vertical MOSFET as well as the vertical MOS Gated Tunnel Diode

MODELLING AND DESIGN OF DIAMOND POWER SEMICONDUCTOR DEVICES

With its remarkable electro-thermal properties such as the highest known thermal conductivity (~22 W/cm∙ K at room temperature) of any material, high hole mobility (>2000 cm2/V∙s), high critical electric field (>10 MV/cm), and large bandgap (5.47 eV), Diamond has overwhelming advantages over Silicon and wide bandgap semiconductors (WBG) for ultra-high voltage and high temperature applications (>3 kV and >450 K, respectively). However, despite its tremendous potential, fabricated devices based on this material have not yet delivered the expected high-performance. This is due to three main reasons: (i) the lack of consistent physical models and design approaches specific to diamond-based devices that could significantly accelerate their development; (ii) the absence of shallow acceptor and donor dopant species which has resulted in poor room temperature performance; (iii) the technological issues of the manufacturing process. With the principal aim of modelling the next generation of diamond devices, this Ph.D dissertation endeavours to numerically model the main electro-thermal properties of diamond devices for power electronic applications. Optimized unipolar mode diamond field effect transistors have been designed by means of finite element simulations and their performance has been assessed against the state-of-the-art diamond FETs. Particular attention is given to the static and dynamic properties of deep dopant levels and their effects in WBG semiconductor-based devices. Moreover, by means of a more global comparison technique and through accurate theoretical analysis, diamond FETs and diodes’ performance have been projected and compared with that of GaN and SiC devices. This work concludes with possible implementations of diamond devices in power converters and provides a roadmap of diamond devices for power electronics. These promising results give a new impetus to the rather small, but growing diamond community and enable future research in the field with the goal of bringing diamond to the commercial world.U.K. Engineering and Physical Sciences Research Council for the University of Cambridge Centre for Doctoral Training under Grant EP/M506485/

Index to 1983 NASA Tech Briefs, volume 8, numbers 1-4

Short announcements of new technology derived from the R&D activities of NASA are presented. These briefs emphasize information considered likely to be transferrable across industrial, regional, or disciplinary lines and are issued to encourage commercial application. This index for 1983 Tech Briefs contains abstracts and four indexes: subject, personal author, originating center, and Tech Brief Number. The following areas are covered: electronic components and circuits, electronic systems, physical sciences, materials, life sciences, mechanics, machinery, fabrication technology, and mathematics and information sciences