Wave-like Decoding of Tail-biting Spatially Coupled LDPC Codes Through Iterative Demapping

For finite coupling lengths, terminated spatially coupled low-density parity-check (SC-LDPC) codes show a non-negligible rate-loss. In this paper, we investigate if this rate loss can be mitigated by tail-biting SC-LDPC codes in conjunction with iterative demapping of higher order modulation formats. Therefore, we examine the BP threshold of different coupled and uncoupled ensembles. A comparison between the decoding thresholds approximated by EXIT charts and the density evolution results of the coupled and uncoupled ensemble is given. We investigate the effect and potential of different labelings for such a set-up using per-bit EXIT curves, and exemplify the method for a 16-QAM system, e.g., using set partitioning labelings. A hybrid mapping is proposed, where different sub-blocks use different labelings in order to further optimize the decoding thresholds of tail-biting codes, while the computational complexity overhead through iterative demapping remains small.Comment: presentat at the International Symposium on Turbo Codes & Iterative Information Processing (ISTC), Brest, Sept. 201

Wave-like Decoding of Tail-biting Spatially Coupled LDPC Codes Through Iterative Demapping

For finite coupling lengths, terminated spatially coupled low-density parity-check (SC-LDPC) codes show a non-negligible rate-loss. In this paper, we investigate if this rate loss can be mitigated by tail-biting SC-LDPC codes in conjunction with iterative demapping of higher order modulation formats. Therefore, we examine the BP threshold of different coupled and uncoupled ensembles. A comparison between the decoding thresholds approximated by EXIT charts and the density evolution results of the coupled and uncoupled ensemble is given. We investigate the effect and potential of different labelings for such a set-up using per-bit EXIT curves, and exemplify the method for a 16-QAM system, e.g., using set partitioning labelings. A hybrid mapping is proposed, where different sub-blocks use different labelings in order to further optimize the decoding thresholds of tail-biting codes, while the computational complexity overhead through iterative demapping remains small.Comment: presentat at the International Symposium on Turbo Codes & Iterative Information Processing (ISTC), Brest, Sept. 201

Near-capacity fixed-rate and rateless channel code constructions

Fixed-rate and rateless channel code constructions are designed for satisfying conflicting design tradeoffs, leading to codes that benefit from practical implementations, whilst offering a good bit error ratio (BER) and block error ratio (BLER) performance. More explicitly, two novel low-density parity-check code (LDPC) constructions are proposed; the first construction constitutes a family of quasi-cyclic protograph LDPC codes, which has a Vandermonde-like parity-check matrix (PCM). The second construction constitutes a specific class of protograph LDPC codes, which are termed as multilevel structured (MLS) LDPC codes. These codes possess a PCM construction that allows the coexistence of both pseudo-randomness as well as a structure requiring a reduced memory. More importantly, it is also demonstrated that these benefits accrue without any compromise in the attainable BER/BLER performance. We also present the novel concept of separating multiple users by means of user-specific channel codes, which is referred to as channel code division multiple access (CCDMA), and provide an example based on MLS LDPC codes. In particular, we circumvent the difficulty of having potentially high memory requirements, while ensuring that each user’s bits in the CCDMA system are equally protected. With regards to rateless channel coding, we propose a novel family of codes, which we refer to as reconfigurable rateless codes, that are capable of not only varying their code-rate but also to adaptively modify their encoding/decoding strategy according to the near-instantaneous channel conditions. We demonstrate that the proposed reconfigurable rateless codes are capable of shaping their own degree distribution according to the nearinstantaneous requirements imposed by the channel, but without any explicit channel knowledge at the transmitter. Additionally, a generalised transmit preprocessing aided closed-loop downlink multiple-input multiple-output (MIMO) system is presented, in which both the channel coding components as well as the linear transmit precoder exploit the knowledge of the channel state information (CSI). More explicitly, we embed a rateless code in a MIMO transmit preprocessing scheme, in order to attain near-capacity performance across a wide range of channel signal-to-ratios (SNRs), rather than only at a specific SNR. The performance of our scheme is further enhanced with the aid of a technique, referred to as pilot symbol assisted rateless (PSAR) coding, whereby a predetermined fraction of pilot bits is appropriately interspersed with the original information bits at the channel coding stage, instead of multiplexing pilots at the modulation stage, as in classic pilot symbol assisted modulation (PSAM). We subsequently demonstrate that the PSAR code-aided transmit preprocessing scheme succeeds in gleaning more information from the inserted pilots than the classic PSAM technique, because the pilot bits are not only useful for sounding the channel at the receiver but also beneficial for significantly reducing the computational complexity of the rateless channel decoder

Ultra-Sparse Non-Binary LDPC Codes for Probabilistic Amplitude Shaping

This work shows how non-binary low-density parity-check codes over GF($2^p$) can be combined with probabilistic amplitude shaping (PAS) (B\"ocherer, et al., 2015), which combines forward-error correction with non-uniform signaling for power-efficient communication. Ultra-sparse low-density parity-check codes over GF(64) and GF(256) gain 0.6 dB in power efficiency over state-of-the-art binary LDPC codes at a spectral efficiency of 1.5 bits per channel use and a blocklength of 576 bits. The simulation results are compared to finite length coding bounds and complemented by density evolution analysis.Comment: Accepted for Globecom 201

Network flow algorithms for wireless networks and design and analysis of rate compatible LDPC codes

While Shannon already characterized the capacity of point-to-point channels back in 1948, characterizing the capacity of wireless networks has been a challenging problem. The deterministic channel model proposed by Avestimehr, etc. (2007 - 1) has been a promising approach for approximating the Gaussian channel capacity and has been widely studied recently. Motivated by this model, an improved combinatorial algorithm is considered for finding the unicast capacity for wireless information flow on such deterministic networks in the first part of this thesis. Our algorithm fully explores the useful combinatorial features intrinsic in the problem. Our improvement applies generally with any size of finite fields associated with the channel model. Comparing with other related algorithms, our improved algorithm has very competitive performance in complexity. In the second part of our work, we consider the design and analysis of rate-compatible LDPC codes. Rate-compatible LDPC codes are basically a family of nested codes, operating at different code rates and all of them can be encoded and decoded using a single encoder and decoder pair. Those properties make rate-compatible LDPC codes a good choice for changing channel conditions, like in wireless communications. The previous work on the design and analysis of LDPC codes are all targeting at a specific code rate and no work is known on the design and analysis of rate-compatible LDPC codes so that the code performance at all code rates in the family is manageable and predictable. In our work, we proposed algorithms for the design and analysis of rate-compatible LDPC codes with good performance and make the code performance at all code rates manageable and predictable. Our work is based on E2RC codes, while our approaches in the design and analysis can be applied more generally not only to E2RC codes, but to other suitable scenarios, like the design of IRA codes. Most encouragingly, we obtain families of rate-compatible codes whose gaps to capacity are at most 0.3 dB across the range of rates when the maximum variable node degree is twenty, which is very promising compared with other existing results

Decoder-in-the-Loop: Genetic Optimization-based LDPC Code Design

LDPC code design tools typically rely on asymptotic code behavior and are affected by an unavoidable performance degradation due to model imperfections in the short length regime. We propose an LDPC code design scheme based on an evolutionary algorithm, the Genetic Algorithm (GenAlg), implementing a "decoder-in-the-loop" concept. It inherently takes into consideration the channel, code length and the number of iterations while optimizing the error-rate of the actual decoder hardware architecture. We construct short length LDPC codes (i.e., the parity-check matrix) with error-rate performance comparable to, or even outperforming that of well-designed standardized short length LDPC codes over both AWGN and Rayleigh fading channels. Our proposed algorithm can be used to design LDPC codes with special graph structures (e.g., accumulator-based codes) to facilitate the encoding step, or to satisfy any other practical requirement. Moreover, GenAlg can be used to design LDPC codes with the aim of reducing decoding latency and complexity, leading to coding gains of up to $0.325$ dB and $0.8$ dB at BLER of $10^{-5}$ for both AWGN and Rayleigh fading channels, respectively, when compared to state-of-the-art short LDPC codes. Also, we analyze what can be learned from the resulting codes and, as such, the GenAlg particularly highlights design paradigms of short length LDPC codes (e.g., codes with degree-1 variable nodes obtain very good results).Comment: in IEEE Access, 201