VLSI Implementation of TDC Architectures Used in PET Imaging Systems

Positron emission tomography (PET) is a medical imaging method based on the measurement of concentrations of positron-emitting radionuclides in a living body. In the PET imaging system, glucose is labeled with a positron-emitting radionuclide and injected intravenously. Then, the positrons move through the tissue and collide with the electrons of the cells in which they interact. As a result of this interaction, two gamma rays are emitted in the opposite direction. Gama rays emitted from cancerous tissue that has retained radioactive glucose are detected through ring-shaped detectors. And the detected signals are converted into an electrical response. Subsequently, these responses are sampled with electronic circuits and recorded as histogram matrix to generate the image set. The gamma rays may not reach the detectors located in the opposite position in equal time. In PETs having TOF characteristics, it is aimed to obtain better positioning information by a method based on the principle of measuring the difference between the reach time of the two photons to detectors. The measurement of the flight time is carried out with TDC structures. The measurement of this time difference at the ps level is directly related to the spatial resolution of the PET system. In this study, 45 nm CMOS VLSI simulations of TDC structures that have various architectural approaches were performed for use in PET systems. With the designed TDC architectures, two gamma photons time reach to detectors have been simulated and the time difference has been successfully digitized. In addition, various performance metrics such as input and output voltages, time resolutions, measurement ranges, and power analysis of TDC architectures have been determined. Proposed Vernier oscillator-based TDC architecture has been reached 25 ps time resolution with a low power consumption of 1.62681 mW at 1V supply voltage.Comment: 8 pages, in Turkish language. 6 figures, conference paper,International Marmara Sciences Congess (IMASCON 2019 SPRING), https://www.imascon.com/dosyalar/imascon2019bahar/imascon_fen_bildiriler_ciltII_bahar_2019.pdf , https://avesis.kocaeli.edu.tr/yayin/99073ee1-45ff-495e-9cab-42de4d0fad71/vlsi-implementation-of-tdc-architectures-used-in-pet-imaging-system

A versatile wearable based on reconfigurable hardware for biomedical measurements

In this work a versatile hardware platform based on reconfigurable devices is presented. This platform it intended for the acquisition of multiple biosignals, only requiring a reconfiguration to switch applications. This prototype has been combined with graphene-based, flexible electrodes to cover the application to different biosignals presented in this paper, which are electrocardiogram, electrooculogram and electromyogram. The features of this system provide to the user and to medical personnel a complete set of diagnosis tools, available both at home and hospitals, to be used as a triage tool and for remote patient monitoring. Additionally, an Android application has been developed for signal processing and data presentation to the user. The results obtained demonstrate the wide range of possibilities in portable/wearable applications of the combination of reconfigurable devices and flexible electronics, especially for the remote monitoring of patients using multiple biosignals of interest. The versatility of this device makes it a complete set of monitoring tools integrated in a reduced size device

Design and built-in characterization of digital-to-time converters for ultra-low power ADPLLs

ESSCIRC 2015 - 41st IEEE European Solid-State Circuits Conference (ESSCIRC), Graz, Austria, 14-18 September 2015The newly proposed phase-prediction counter-based ADPLL has achieved a wireless standard-compliant performance at ultra-low power consumption. The digital-to-time converter (DTC) is the key enabler but is nonlinearity can easily create fractional spurs. This paper analyzes the effect of the DTC nonlinearity on in-band fractional spurs and proposes a method to characterize it in a built-in fashion by means of a fine-resolution ΔΣ TDC that forms an outer loop with the DTC. The TDC is realized in 40nm CMOS and exhibits only 1.8ps rms of random jitter.IMEC, Belgiu

Current-mode processing based Temperature-to-Digital Converters for MEMS applications

This thesis presents novel Temperature-to-Digital Converters (TDCs) designed and fabricated in CMOS technology. These integrated smart temperature sensing circuits are widely employed in the Micro-Electro-Mechanical Systems (MEMS) field in order to mitigate the impact of the ambient temperature on their performance. In this framework, the increasingly stringent demands of the market have led the cost-effectiveness specification of these compensation solutions to an higher and higher level, directly translating into the requirement of more and more compact designs (< 0.1 mm²); in addition to this, considering that the great majority of the systems whose thermal drift needs to be compensated is battery supplied, ultra-low energy-per-conversion (< 10 nJ) is another requirement of primary importance. This thesis provides a detailed description of two different test-chips (mas fuerte and es posible) that have been designed with this orientation and that are the result of three years of research activity; for both devices, the conception, design, layout and testing phases are all described in detail and are supported by simulation and measurement results.This thesis presents novel Temperature-to-Digital Converters (TDCs) designed and fabricated in CMOS technology. These integrated smart temperature sensing circuits are widely employed in the Micro-Electro-Mechanical Systems (MEMS) field in order to mitigate the impact of the ambient temperature on their performance. In this framework, the increasingly stringent demands of the market have led the cost-effectiveness specification of these compensation solutions to an higher and higher level, directly translating into the requirement of more and more compact designs (< 0.1 mm²); in addition to this, considering that the great majority of the systems whose thermal drift needs to be compensated is battery supplied, ultra-low energy-per-conversion (< 10 nJ) is another requirement of primary importance. This thesis provides a detailed description of two different test-chips (mas fuerte and es posible) that have been designed with this orientation and that are the result of three years of research activity; for both devices, the conception, design, layout and testing phases are all described in detail and are supported by simulation and measurement results

Custom Memory Design for Logic-in-Memory: Drawbacks and Improvements over Conventional Memories

The speed of modern digital systems is severely limited by memory latency (the “Memory Wall” problem). Data exchange between Logic and Memory is also responsible for a large part of the system energy consumption. Logic-in-Memory (LiM) represents an attractive solution to this problem. By performing part of the computations directly inside the memory the system speed can be improved while reducing its energy consumption. LiM solutions that offer the major boost in performance are based on the modification of the memory cell. However, what is the cost of such modifications? How do these impact the memory array performance? In this work, this question is addressed by analysing a LiM memory array implementing an algorithm for the maximum/minimum value computation. The memory array is designed at physical level using the FreePDK 45nm CMOS process, with three memory cell variants, and its performance is compared to SRAM and CAM memories. Results highlight that read and write operations performance is worsened but in-memory operations result to be very efficient: a 55.26% reduction in the energy-delay product is measured for the AND operation with respect to the SRAM read one. Therefore, the LiM approach represents a very promising solution for low-density and high-performance memories

A fully integrated 28nm Bluetooth low-energy transmitter with 36% system efficiency at 3dBm

ESSCIRC 2015 - 41st European Solid-State Circuits Conference (ESSCIRC), Graz, Austria, 14 - 18 September 2015We propose a new transmitter (TX) architecture for ultra-low power radios. An all-digital PLL employs a digitally controlled oscillator with switching current sources to reduce supply voltage and power without sacrificing its phase noise and startup margins. It also reduces 1/f noise allowing the ADPLL, after settling, to reduce its sampling rate or shut it off entirely during direct DCO data modulation. The switching power amplifier integrates its matching network while operating in class-E/F2 to maximally enhance its efficiency. The transmitter is realized in 28nm CMOS and satisfies all metal density and other manufacturing rules. It consumes 3.6 mW/5.5mW while delivering 0 dBm/3dBm RF power in Bluetooth Low-Energy.TSM

Delay-based true random number generator in sub-nanomillimeter IoT devices

True Random Number Generators (TRNGs) use physical phenomenon as their source of randomness. In electronics, one of the most popular structures to build a TRNG is constructed based on the circuits that form propagation delays, such as a ring oscillator, shift register, and routing paths. This type of TRNG has been well-researched within the current technology of electronics. However, in the future, where electronics will use sub-nano millimeter (nm) technology, the components become smaller and work on near-threshold voltage (NTV). This condition has an effect on the timing-critical circuit, as the distribution of the process variation becomes non-gaussian. Therefore, there is an urge to assess the behavior of the current delay-based TRNG system in sub-nm technology. In this paper, a model of TRNG implementation in sub-nm technology was created through the use of a specific Look-Up Table (LUT) in the Field-Programmable Gate Array (FPGA), known as SRL16E. The characterization of the TRNG was presented and it shows a promising result, in that the delay-based TRNG will work properly, with some constraints in sub-nm technolog

Analog and mixed-signal design and test techniques for improved reliability

The relentless evolution of semiconductor technology has led to a pervasive reliance on integrated circuits (ICs) across an array of applications, from consumer electronics to safety-critical systems in automotive and medical devices. Ensuring the reliability and robustness of these ICs has become paramount. This dissertation addresses the growing need for defect-oriented testing in analog and mixed-signal (AMS) circuits, introducing a novel digital-like methodology. It emphasizes breaking down complex AMS circuits into smaller, manageable subcircuits, which are rigorously examined using purely digital monitors and injectors. The methodology is resource-efficient, optimizing existing circuit resources to minimize area overhead and power consumption. A significant achievement lies in the development of a Built-In Self-Test (BIST) for a 12-bit Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC), showcasing the approach's effectiveness and flexibility. Additionally, this dissertation pioneers a smart sensor design approach that reduces dependence on intricate device models, thereby ensuring high performance across a broad range of operating conditions. A case study on a temperature-to-digital converter (TDC) design demonstrates its capability to function reliably over an extensive temperature range. The methodology optimizes parameters, allowing energy-efficient sensor designs that meet industry standards while minimizing silicon area and power consumption. These works signify a dedicated commitment to advancing the reliability and functional safety of analog and mixed-signal circuits, contributing to the evolving landscape of IC design

Low Power Memory/Memristor Devices and Systems

This reprint focusses on achieving low-power computation using memristive devices. The topic was designed as a convenient reference point: it contains a mix of techniques starting from the fundamental manufacturing of memristive devices all the way to applications such as physically unclonable functions, and also covers perspectives on, e.g., in-memory computing, which is inextricably linked with emerging memory devices such as memristors. Finally, the reprint contains a few articles representing how other communities (from typical CMOS design to photonics) are fighting on their own fronts in the quest towards low-power computation, as a comparison with the memristor literature. We hope that readers will enjoy discovering the articles within

Electronics for Sensors

The aim of this Special Issue is to explore new advanced solutions in electronic systems and interfaces to be employed in sensors, describing best practices, implementations, and applications. The selected papers in particular concern photomultiplier tubes (PMTs) and silicon photomultipliers (SiPMs) interfaces and applications, techniques for monitoring radiation levels, electronics for biomedical applications, design and applications of time-to-digital converters, interfaces for image sensors, and general-purpose theory and topologies for electronic interfaces