10-GHz fully differential Sallen–Key lowpass biquad filters in 55nm SiGe BICMOS technology

Multi-GHz lowpass filters are key components for many RF applications and are required for the implementation of integrated high-speed analog-to-digital and digital-to-analog converters and optical communication systems. In the last two decades, integrated filters in the Multi-GHz range have been implemented using III-V or SiGe technologies. In all cases in which the size of passive components is a concern, inductorless designs are preferred. Furthermore, due to the recent development of high-speed and high-resolution data converters, highly linear multi-GHz filters are required more and more. Classical open loop topologies are not able to achieve high linearity, and closed loop filters are preferred in all applications where linearity is a key requirement. In this work, we present a fully differential BiCMOS implementation of the classical Sallen Key filter, which is able to operate up to about 10 GHz by exploiting both the bipolar and MOS transistors of a commercial 55-nm BiCMOS technology. The layout of the biquad filter has been implemented, and the results of post-layout simulations are reported. The biquad stage exhibits excellent SFDR (64 dB) and dynamic range (about 50 dB) due to the closed loop operation, and good power efficiency (0.94 pW/Hz/pole) with respect to comparable active inductorless lowpass filters reported in the literature. Moreover, unlike other filters, it exploits the different active devices offered by commercial SiGe BiCMOS technologies. Parametric and Monte Carlo simulations are also included to assess the robustness of the proposed biquad filter against PVT and mismatch variations

AN EFFICIENT FULLY DIFFERENTIAL VOLTAGE COMPARATOR

With the compactness of the devices, the circuits are required with less delay, less area and less power consumption. An efficient fully digital-in-notion differential voltage comparator with the opamp-less approach is implemented in this paper. This comparator detects a small input voltage difference, i.e., resolution of this comparator is 8-bits and amplifies the output to either of the two different logic levels high or low, i.e., 1 or 0 respectively. Though dynamic latched comparators are quite attractive, they suffer from high power consumption and large offset voltages. In addition to the low power consumption, this comparator is extremely cost-effective as an analogue circuit has been designed digitally and fabricated in a digital process. The comparator is designed and implemented in the Cadence Virtuoso tool using SCL 180 nm Complementary Metal Oxide Semiconductor (CMOS) digital process at a supply of 1.8 V and a load capacitance of 1 pF

Current-mode processing based Temperature-to-Digital Converters for MEMS applications

This thesis presents novel Temperature-to-Digital Converters (TDCs) designed and fabricated in CMOS technology. These integrated smart temperature sensing circuits are widely employed in the Micro-Electro-Mechanical Systems (MEMS) field in order to mitigate the impact of the ambient temperature on their performance. In this framework, the increasingly stringent demands of the market have led the cost-effectiveness specification of these compensation solutions to an higher and higher level, directly translating into the requirement of more and more compact designs (< 0.1 mm²); in addition to this, considering that the great majority of the systems whose thermal drift needs to be compensated is battery supplied, ultra-low energy-per-conversion (< 10 nJ) is another requirement of primary importance. This thesis provides a detailed description of two different test-chips (mas fuerte and es posible) that have been designed with this orientation and that are the result of three years of research activity; for both devices, the conception, design, layout and testing phases are all described in detail and are supported by simulation and measurement results.This thesis presents novel Temperature-to-Digital Converters (TDCs) designed and fabricated in CMOS technology. These integrated smart temperature sensing circuits are widely employed in the Micro-Electro-Mechanical Systems (MEMS) field in order to mitigate the impact of the ambient temperature on their performance. In this framework, the increasingly stringent demands of the market have led the cost-effectiveness specification of these compensation solutions to an higher and higher level, directly translating into the requirement of more and more compact designs (< 0.1 mm²); in addition to this, considering that the great majority of the systems whose thermal drift needs to be compensated is battery supplied, ultra-low energy-per-conversion (< 10 nJ) is another requirement of primary importance. This thesis provides a detailed description of two different test-chips (mas fuerte and es posible) that have been designed with this orientation and that are the result of three years of research activity; for both devices, the conception, design, layout and testing phases are all described in detail and are supported by simulation and measurement results

Miniature high dynamic range time-resolved CMOS SPAD image sensors

Since their integration in complementary metal oxide (CMOS) semiconductor technology in 2003, single photon avalanche diodes (SPADs) have inspired a new era of low cost high integration quantum-level image sensors. Their unique feature of discerning single photon detections, their ability to retain temporal information on every collected photon and their amenability to high speed image sensor architectures makes them prime candidates for low light and time-resolved applications. From the biomedical field of fluorescence lifetime imaging microscopy (FLIM) to extreme physical phenomena such as quantum entanglement, all the way to time of flight (ToF) consumer applications such as gesture recognition and more recently automotive light detection and ranging (LIDAR), huge steps in detector and sensor architectures have been made to address the design challenges of pixel sensitivity and functionality trade-off, scalability and handling of large data rates. The goal of this research is to explore the hypothesis that given the state of the art CMOS nodes and fabrication technologies, it is possible to design miniature SPAD image sensors for time-resolved applications with a small pixel pitch while maintaining both sensitivity and built -in functionality. Three key approaches are pursued to that purpose: leveraging the innate area reduction of logic gates and finer design rules of advanced CMOS nodes to balance the pixel’s fill factor and processing capability, smarter pixel designs with configurable functionality and novel system architectures that lift the processing burden off the pixel array and mediate data flow. Two pathfinder SPAD image sensors were designed and fabricated: a 96 × 40 planar front side illuminated (FSI) sensor with 66% fill factor at 8.25μm pixel pitch in an industrialised 40nm process and a 128 × 120 3D-stacked backside illuminated (BSI) sensor with 45% fill factor at 7.83μm pixel pitch. Both designs rely on a digital, configurable, 12-bit ripple counter pixel allowing for time-gated shot noise limited photon counting. The FSI sensor was operated as a quanta image sensor (QIS) achieving an extended dynamic range in excess of 100dB, utilising triple exposure windows and in-pixel data compression which reduces data rates by a factor of 3.75×. The stacked sensor is the first demonstration of a wafer scale SPAD imaging array with a 1-to-1 hybrid bond connection. Characterisation results of the detector and sensor performance are presented. Two other time-resolved 3D-stacked BSI SPAD image sensor architectures are proposed. The first is a fully integrated 5-wire interface system on chip (SoC), with built-in power management and off-focal plane data processing and storage for high dynamic range as well as autonomous video rate operation. Preliminary images and bring-up results of the fabricated 2mm² sensor are shown. The second is a highly configurable design capable of simultaneous multi-bit oversampled imaging and programmable region of interest (ROI) time correlated single photon counting (TCSPC) with on-chip histogram generation. The 6.48μm pitch array has been submitted for fabrication. In-depth design details of both architectures are discussed

Radiation Tolerant Electronics, Volume II

Research on radiation tolerant electronics has increased rapidly over the last few years, resulting in many interesting approaches to model radiation effects and design radiation hardened integrated circuits and embedded systems. This research is strongly driven by the growing need for radiation hardened electronics for space applications, high-energy physics experiments such as those on the large hadron collider at CERN, and many terrestrial nuclear applications, including nuclear energy and safety management. With the progressive scaling of integrated circuit technologies and the growing complexity of electronic systems, their ionizing radiation susceptibility has raised many exciting challenges, which are expected to drive research in the coming decade.After the success of the first Special Issue on Radiation Tolerant Electronics, the current Special Issue features thirteen articles highlighting recent breakthroughs in radiation tolerant integrated circuit design, fault tolerance in FPGAs, radiation effects in semiconductor materials and advanced IC technologies and modelling of radiation effects

Ultra Low Noise CMOS Image Sensors

CMOS Image Sensors (CIS) overtook the charge coupled devices (CCDs) in low noise performance. Photoelectron counting capability is the next step for CIS for ultimate low light performance and new imaging paradigms. This work presents a review of CMOS image sensors based on pinned photo diodes (PPDs). The latter includes the historical background, the PPD physics and the readout chain circuits used for low-noise performance. The physical mechanisms behind the random fluctuations affecting the signal at different levels of conventional CIS readout chains are reviewed and clarified. This thesis dedicates a particular focus to the readout circuit noise given that it precludes photoelectron counting in conventional CIS. A detailed analytical calculation of the temporal read noise (TRN) in conventional CIS readout chain is presented. The latter suggests different noise reduction techniques at process and circuit design level. Among the noise reduction techniques suggested by the analytical noise calculation, the increase of the oxide capacitance by using a thin oxide in-pixel amplifying transistor, for low 1/f noise, is suggested for the first time. A test chip designed in a 180 nm CIS process and embedding optimized readout chains exploiting the new pixels together with state-of-the-art 4T pixels optimized at process level for low 1/f noise. A mean input-referred noise of 0.4 e-rms has been measured. Compared with the state-of-the-art pixels, also present onto the test chip, the mean RMS noise is divided by more than 2. Based on these encouraging result, a full VGA (640H×480V) imager has been integrated in a standard CIS process. The presented imager relies on a 4T pixel of 6.5 µm pitch with a properly sized and biased thin oxide PMOS source follower. A full characterization of the proposed image sensor, at room temperature, is presented. The sensor chip features an input-referred noise histogram from 0.25 e-rms to a few e-rms peaking at 0.48 e-rms. This sub-0.5 electron noise performance is obtained with a full well capacity of 6400 e- and a frame rate that can go up to 80 fps. The VGA imager also features a fixed pattern noise as low as 0.77%, a lag of 0.1% and a dark current of 5.6 e-/s. Correlated multiple sampling (CMS) is a noise reduction technique commonly used in low noise CIS. This work presents an original design for CMS based on a passive switched-capacitor network, with a minimum number of capacitors. The proposed circuit requires no additional active circuitry, has no impact on the output dynamic range and does not need multiple analog-to-digital conversions. It was verified with transient noise simulations and shows a noise reduction in perfect agreement with ideal CMS. For a future perspective, the impact of the technology downscale on CIS sensitivity from an electronic read noise aspect is investigated. Active imaging in the Terahertz (THz) band is an emerging technology. Source modulation combined with a selective filtering can be used to reduce the noise in CMOS THz imagers. This work presents the first integration of a 1 kpixel CMOS THz imager integrating, in each pixel, a metal antenna with a MOS rectifier, low noise amplification and highly selective filtering, based on a switch-capacitor N-path filter combined with a broad band Gm-C filter. The latter has been tested successfully. An input-referred noise of 0.2 µV RMS corresponding to a total noise equivalent THz power of 0.6 nW at 270 GHz and 0.8 nW at 600 GHz