Chaotic Oscillations in CMOS Integrated Circuits

Chaos is a purely mathematical term, describing a signal that is aperiodic and sensitive to initial conditions, but deterministic. Yet, engineers usually see it as an undesirable effect to be avoided in electronics. The first part of the dissertation deals with chaotic oscillation in complementary metal-oxide-semiconductor integrated circuits (CMOS ICs) as an effect behavior due to high power microwave or directed electromagnetic energy source. When the circuit is exposed to external electromagnetic sources, it has long been conjectured that spurious oscillation is generated in the circuits. In the first part of this work, we experimentally and numerically demonstrate that these spurious oscillations, or out-of-band oscillations are in fact chaotic oscillations. In the second part of the thesis, we exploit a CMOS chaotic oscillator in building a cryptographic source, a random number generator. We first demonstrate the presence of chaotic oscillation in standard CMOS circuits. At radio frequencies, ordinary digital circuits can show unexpected nonlinear responses. We evaluate a CMOS inverter coupled with electrostatic discharging (ESD) protection circuits, designed with 0.5 μm CMOS technology, for their chaotic oscillations. As the circuit is driven by a direct radio frequency injection, it exhibits a chaotic dynamics, when the input frequency is higher than the typical maximum operating frequency of the CMOS inverter. We observe an aperiodic signal, a broadband spectrum, and various bifurcations in the experimental results. We analytically discuss the nonlinear physical effects in the given circuit : ESD diode rectification, DC bias shift due to a non-quasi static regime operation of the ESD PN-junction diode, and a nonlinear resonant feedback current path. In order to predict these chaotic dynamics, we use a transistor-based model, and compare the model's performance with the experimental results. In order to verify the presence of chaotic oscillations mathematically, we build on an ordinary differential equation model with the circuit-related nonlinearities. We then calculate the largest Lyapunov exponents to verify the chaotic dynamics. The importance of this work lies in investigating chaotic dynamics of standard CMOS ICs that has long been conjectured. In doing so, we experimentally and numerically give evidences for the presence of chaotic oscillations. We then report on a random number generator design, in which randomness derives from a Boolean chaotic oscillator, designed and fabricated as an integrated circuit. The underlying physics of the chaotic dynamics in the Boolean chaotic oscillator is given by the Boolean delay equation. According to numerical analysis of the Boolean delay equation, a single node network generates chaotic oscillations when two delay inputs are incommensurate numbers and the transition time is fast. To test this hypothesis physically, a discrete Boolean chaotic oscillator is implemented. Using a CMOS 0.5 μm process, we design and fabricate a CMOS Boolean chaotic oscillator which consists of a core chaotic oscillator and a source follower buffer. Chaotic dynamics are verified using time and frequency domain analysis, and the largest Lyapunov exponents are calculated. The measured bit sequences do make a suitable randomness source, as determined via National Institute of Standards and Technology (NIST) standard statistical tests version 2.1

Equalization of Third-Order Intermodulation Products in Wideband Direct Conversion Receivers

This paper reports a SAW-less direct-conversion receiver which utilizes a mixed-signal feedforward path to regenerate and adaptively cancel IM3 products, thus accomplishing system-level linearization. The receiver system performance is dominated by a custom integrated RF front end implemented in 130-nm CMOS and achieves an uncorrected out-of-band IIP3 of -7.1 dBm under the worst-case UMTS FDD Region 1 blocking specifications. Under IM3 equalization, the receiver achieves an effective IIP3 of +5.3 dBm and meets the UMTS BER sensitivity requirement with 3.7 dB of margin

Optimal design of a 2.4 GHz CMOS low noise amplifier

In most RF receivers, the Low Noise Amplifier (LNA) is normally the first component, whose performance is very critical. For the LNA architecture that uses source degeneration inductors and cascode topology, the performance depends largely on the performance of the inductors. All the parasitics associated with the inductors should be thoroughly analyzed and taken into consideration while designing the LNA. The work presented in this thesis can be broadly classified as follows: optimization of the LNA design with respect to all the parasitics associated with the on-chip spiral inductors, modeling high performance inductors, which are embedded in the silicon substrate and analysis of parasitic effects from the Electro Static Discharge (ESD) protection circuitry on the performance of the LNA. A methodology has been developed such that the LNA design can be optimized in the presence of an ESD protection circuitry in order to achieve the required input impedance match. This optimization procedure is presented for all possible placements of the ESD protection circuitry at the input of the LNA, that is, with respect to the gate inductor being realized on-chip or off-chip or a combination of on-chip and off-chip inductors. The thesis presents the procedure to vary the source inductance and gate inductance values in the presence of parasitic ESD capacitance in order to optimize LNA design such that the required input impedance match is maintained

Linearity vs. Power Consumption of CMOS LNAs in LTE Systems

This paper presents a study of linearity in wideband CMOS low noise amplifiers (LNA) and its relationship to power consumption in context of Long Term Evolution (LTE) system. Using proposed figure of merit to compare 35 state-of-the-art LNA circuits published in recent years, the paper shows a proportional but relatively weak dependence between amplifier performance (that is combined linearity, noise figure and gain) with power consumption. As a result, the predicted increase of LNA performance, necessary to satisfy stringent linearity specifications of LTE standard, may require a significant increase in power, a critical budget planning aspect for both handheld devices and base stations operating in small cells

RFID Logic circuit with oxide TFTs modeled by genetic algorithms

Nos últimos anos, a necessidade por técnicas de identificação com velocidades de leitura superiores e maior flexibilidade relativamente à memória e programabilidade, levaram ao desenvolvimento de tecnologias de identificação de rádio frequência (RFID). Esta tecnologia já provou o seu valor no futuro da Internet das coisas (IoT), ao permitir a possibilidade de marcar qualquer tipo de produto facilmente e com baixo custo por etiqueta, enquanto possibilita a conexão deste tipo de etiquetas com smartphones para aumentar a ligação entre os dispositivos RFID e a vida quotidiana. Além disto, a introdução de transístores de filme fino (TFT) de óxidos amorfos em circuitos RFID, abre um novo mundo de aplicações, visto que este tipo de dispositivos permite o uso de substratos transparentes e/ou flexíveis, devido à possibilidade de usar baixas temperaturas durante o processo de fabrico para este tipo de transístores. Neste trabalho, foi usado o Modelo a-Si Nível 61 com a ajuda de algoritmos genéticos para criar modelos de transístores de a-IGZO produzidos com um dielétrico de porta depositado por métodos de solução usando spin-coating. Com estes modelos, foi dimensionado um circuito digital de RFID, usando uma topologia em que o transístor de carga está em configuração de díodo, para ler uma memória ROM de 16-bit e posteriormente codificar o sinal através de uma codificação de Manchester com uma taxa de transferência de 14 kbit/s. Este tipo de circuitos utilizando substratos transparentes e/ou flexíveis pode possibilitar no futuro a criação de embalagens inteligentes para bens domésticos e a posterior integração numa configuração de frigoríficos inteligentes. Isto significa que poderá ser possível uma pessoa ser avisada quando é necessário comprar um produto ou quando ultrapassa o prazo de validade.In recent years, the need for identification techniques, with faster reading speed and more flexibility regarding memory and programmability, led to the development of Radio Frequency Identification technologies. This technology has already proven to be essential in the future of Internet-of-Things, by allowing the possibility of tagging any type of product easily and at low cost per tag, while also allowing the interface of these tags, with common smartphones to increase the connectivity of RFID devices in daily life. Furthermore, the introduction of amorphous IGZO thin film transistors in RFID circuits, opens a new world of applications since this type of devices allows the use of transparent and/or flexible substrates, due to the low temperatures required during the fabrication process. In this work, it was used the a-Si Level 61 TFT Model together with genetic algorithms, to model a-IGZO transistors produced, with a gate dielectric deposited by a solution method using spin coating. With these models, it was designed an RFID logic circuit, which employs diode connected structures, to read a 16-bit Read Only Memory and encode the signal using a Manchester encoding technique, with a data rate of 14 kbit/s. These types of circuits using transparent and/or flexible substrates could allow, in the future, the creation of smart packaging for regular house goods and integrate it in a smart fridge configuration. Meaning that, it could be possible to a person either to be advised when to buy a certain item or when it reaches the expiration date

Analog-Digital System Modeling for Electromagnetic Susceptibility Prediction

The thesis is focused on the noise susceptibility of communication networks. These analog-mixed signal systems operate in an electrically noisy environment, in presence of multiple equipments connected by means of long wiring. Every module communicates using a transceiver as an interface between the local digital signaling and the data transmission through the network. Hence, the performance of the IC transceiver when affected by disturbances is one of the main factors that guarantees the EM immunity of the whole equipment. The susceptibility to RF and transient disturbances is addressed at component level on a CAN transceiver as a test case, highlighting the IC features critical for noise immunity. A novel procedure is proposed for the IC modeling for mixed-signal immunity simulations of communication networks. The procedure is based on a gray-box approach, modeling IC ports with a physical circuit and the internal links with a behavioural block. The parameters are estimated from time and frequency domain measurements, allowing accurate and efficient reproduction of non-linear device switching behaviours. The effectiveness of the modeling process is verified by applying the proposed technique to a CAN transceiver, involved in a real immunity test on a data communication link. The obtained model is successfully implemented in a commercial solver to predict both the functional signals and the RF noise immunity at component level. The noise immunity at system level is then evaluated on a complete communication network, analyzing the results of several tests on a realistic CAN bus. After developing models for wires and injection probes, a noise immunity test in avionic environment is carried out in a simulation environment, observing good overall accuracy and efficiency

Design, Characterization And Analysis Of Electrostatic Discharge (esd) Protection Solutions In Emerging And Modern Technologies

Electrostatic Discharge (ESD) is a significant hazard to electronic components and systems. Based on a specific processing technology, a given circuit application requires a customized ESD consideration that includes the devices’ operating voltage, leakage current, breakdown constraints, and footprint. As new technology nodes mature every 3-5 years, design of effective ESD protection solutions has become more and more challenging due to the narrowed design window, elevated electric field and current density, as well as new failure mechanisms that are not well understood. The endeavor of this research is to develop novel, effective and robust ESD protection solutions for both emerging technologies and modern complementary metal–oxide–semiconductor (CMOS) technologies. The Si nanowire field-effect transistors are projected by the International Technology Roadmap for Semiconductors as promising next-generation CMOS devices due to their superior DC and RF performances, as well as ease of fabrication in existing Silicon processing. Aiming at proposing ESD protection solutions for nanowire based circuits, the dimension parameters, fabrication process, and layout dependency of such devices under Human Body Mode (HBM) ESD stresses are studied experimentally in company with failure analysis revealing the failure mechanism induced by ESD. The findings, including design methodologies, failure mechanism, and technology comparisons should provide practical knowhow of the development of ESD protection schemes for the nanowire based integrated circuits. Organic thin-film transistors (OTFTs) are the basic elements for the emerging flexible, printable, large-area, and low-cost organic electronic circuits. Although there are plentiful studies focusing on the DC stress induced reliability degradation, the operation mechanism of OTFTs iv subject to ESD is not yet available in the literature and are urgently needed before the organic technology can be pushed into consumer market. In this work, the ESD operation mechanism of OTFT depending on gate biasing condition and dimension parameters are investigated by extensive characterization and thorough evaluation. The device degradation evolution and failure mechanism under ESD are also investigated by specially designed experiments. In addition to the exploration of ESD protection solutions in emerging technologies, efforts have also been placed in the design and analysis of a major ESD protection device, diodetriggered-silicon-controlled-rectifier (DTSCR), in modern CMOS technology (90nm bulk). On the one hand, a new type DTSCR having bi-directional conduction capability, optimized design window, high HBM robustness and low parasitic capacitance are developed utilizing the combination of a bi-directional silicon-controlled-rectifier and bi-directional diode strings. On the other hand, the HBM and Charged Device Mode (CDM) ESD robustness of DTSCRs using four typical layout topologies are compared and analyzed in terms of trigger voltage, holding voltage, failure current density, turn-on time, and overshoot voltage. The advantages and drawbacks of each layout are summarized and those offering the best overall performance are suggested at the en