Speech filtering for improving intelligibility in noisy transients

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis.Includes bibliographical references.Hearing impairment is a problem that affects a large percentage of the population. Cochlear implants allow those with profound or total hearing loss to regain some hearing by stimulating auditory nerve fibers with implanted electrodes, in response to sound picked up by an external microphone. The signal processing chain from microphone input to stimulation output is an important factor in the overall speech intelligibility of the implant system. This thesis work improves on an existing ultra-low-power cochlear implant system by utilizing an improved noise and power efficient bandpass filter bank to implement a novel frequency-selective gain control algorithm capable of reducing, and in some cases removing, loud transient noises, thereby improving speech intelligibility. This gain control algorithm takes advantage of the inherent frequency-specific gain control afforded by the improved bandpass filter topology. This contribution makes an improvement to the existing state-of-the-art system in both power efficiency and performance.by Andrew Lewine.M.Eng

Floating-Gate Design and Linearization for Reconfigurable Analog Signal Processing

Analog and mixed-signal integrated circuits have found a place in modern electronics design as a viable alternative to digital pre-processing. With metrics that boast high accuracy and low power consumption, analog pre-processing has opened the door to low-power state-monitoring systems when it is utilized in place of a power-hungry digital signal-processing stage. However, the complicated design process required by analog and mixed-signal systems has been a barrier to broader applications. The implementation of floating-gate transistors has begun to pave the way for a more reasonable approach to analog design. Floating-gate technology has widespread use in the digital domain. Analog and mixed-signal use of floating-gate transistors has only become a rising field of study in recent years. Analog floating gates allow for low-power implementation of mixed-signal systems, such as the field-programmable analog array, while simultaneously opening the door to complex signal-processing techniques. The field-programmable analog array, which leverages floating-gate technologies, is demonstrated as a reliable replacement to signal-processing tasks previously only solved by custom design. Living in an analog world demands the constant use and refinement of analog signal processing for the purpose of interfacing with digital systems. This work offers a comprehensive look at utilizing floating-gate transistors as the core element for analog signal-processing tasks. This work demonstrates the floating gate\u27s merit in large reconfigurable array-driven systems and in smaller-scale implementations, such as linearization techniques for oscillators and analog-to-digital converters. A study on analog floating-gate reliability is complemented with a temperature compensation scheme for implementing these systems in ever-changing, realistic environments

Biomimetic cochlea filters : from modelling, design to analogue VLSI implementation

This thesis presents a novel biomimetic cochlea filter which closely resembles the biological cochlea behaviour. The filter is highly feasible for analogue very-large-scale integration (VLSI) circuits, which leads to a micro-watt-power and millimetre-sized hardware implementation. By virtue of such features, the presented filter contributes to a solid foundation for future biologically-inspired audio signal processors. Unlike existing works, the presented filter is developed by taking direct inspirations from the physiologically measured results of the biological cochlea. Since the biological cochlea has prominently different characteristics of frequency response from low to high frequencies, the biomimetic cochlea filter is built by cascading three sub-filters accordingly: a 2nd-order bandpass filter for the constant gentle low-frequency response, a 2nd-order tunable low-pass filter for the variable and selective centre frequency response and a 5th-order elliptic filter for the ultra-steep roll-off at stop-band. As a proof of concept, a biomimetic cochlea filter bank is built to process audio signals, which demonstrates the highly discriminative spectral decomposition and high-resolution time-frequency analysis capabilities similar to the biological cochlea. The filter has simple representation in the Laplace domain which leads to a convenient analogue circuit realisation. A floating-active-inductor circuit cell is developed to build the corresponding RLC ladder for each of the three sub-filters. The circuits are designed based on complementary metal-oxide-semiconductor (CMOS) transistors for VLSI implementation. Non-ideal factors of CMOS transistors including parasitics, noise and mismatches are extensively analysed and consciously considered in the circuit design. An analogue VLSI chip is successfully fabricated using 0.35μ m CMOS process. The chip measurements demonstrate that the centre frequency response of the filter has about 20 dB wide gain tuning range and a high quality factor reaching maximally over 19. The filter has a 20 dB/decade constant gentle low-frequency tail and an over 300 dB/decade sharp stop-band roll-off slope. The measured results agree with the filter model expectations and are comparable with the biological cochlea characteristics. Each filter channel consumes as low as 59.5 ~90μ Wpower and occupies only 0.9 mm2 area. Besides, the biomimetic cochlea filter chip is characterised from a wide range of angles and the experimental results cover not only the auditory filter specifications but also the integrated circuit design considerations. Furthermore, following the progressive development of the acoustic resonator based on microelectro- mechanical systems (MEMS) technology, a MEMS-CMOS implementation of the proposed filter becomes possible in the future. A key challenge for such implementation is the low sensing capacitance of the MEMS resonator which suffers significantly from sensitivity degradation due to the parasitic capacitance. A novel MEMS capacitive interface circuit chip is additionally developed to solve this issue. As shown in the chip results, the interface circuit is able to cancel the parasitic capacitance and increase the sensitivity of capacitive sensors by 35 dB without consuming any extra power. Besides, the chopper-stabilisation technique is employed which effectively reduces the circuit flicker noise and offsets. Due to these features, the interface circuit chip is capable of converting a 7.5 fF capacitance change of a 1-Volt-biased 0.5 pF capacitive sensor pair into a 0.745 V signal-conditioned output while consuming only 165.2μ W power

Nonlinearity and noise modeling of operational transconductance amplifiers for continuous time analog filters

A general framework for performance optimization of continuous-time OTA-C (Operational Transconductance Amplifier-Capacitor) filters is proposed. Efficient procedures for evaluating nonlinear distortion and noise valid for any filter of arbitrary order are developed based on the matrix description of a general OTA-C filter model . Since these procedures use OTA macromodels, they can be used to obtain the results significantly faster than transistor-level simulation. In the case of transient analysis, the speed-up may be as much as three orders of magnitude without almost no loss of accuracy. This makes it possible to carry out direct numerical optimization of OTA-C filters with respect to important characteristics such as noise performance, THD, IM3, DR or SNR. On the other hand, the general OTA-C filter model allows us to apply matrix transforms that manipulate (rescale) filter element values and/or change topology without changing its transfer function. The above features are a basis to build automated optimization procedures for OTA-C filters. In particular, a systematic optimization procedure using equivalence transformations is proposed. The research also proposes suitable software implementations of the optimization process. The first part of the research proposes a general performance optimization procedure and to verify the process two application type examples are mentioned. An application example of the proposed approach to optimal block sequencing and gain distribution of 8th order cascade Butterworth filter (for two variants of OTA topologies) is given. Secondly the modeling tool is used to select the best suitable topology for a 5th order Bessel Low Pass Filter. Theoretical results are verified by comparing to transistor-level simulation withCADENCE. For the purpose of verification, the filters have also been fabricated in standard 0.5mm CMOS process. The second part of the research proposes a new linearization technique to improve the linearity of an OTA using an Active Error Feedforward technique. Most present day applications require very high linear circuits combined with low noise and low power consumption. An OTA based biquad filter has also been fabricated in 0.35mm CMOS process. The measurement results for the filter and the stand alone OTA have been discussed. The research focuses on these issues

Resource-efficient algorithms and circuits for highly-scalable BMI channel architectures

The study of the human brain has for long fascinated mankind. This organ that controls all cognitive processes and physical actions remains, to this day, among the least understood biological systems. Several billions of neurons form intricate interconnected networks communicating information through through complex electrochemical activities. Electrode arrays, such as for EEG, ECoG, and MEAs (microelectrode arrays), have enabled the observation of neural activity through recording of these electrical signals for both investigative and clinical applications. Although MEAs are widely considered the most invasive such method for recording, they do however provide highest resolution (both spatially and temporally). Due to close proximity, each microelectrode can pick up spiking activity from multiple neurons. This thesis focuses on the design and implementation of novel circuits and systems suitable for high channel count implantable neural interfaces. Implantability poses stringent requirements on the design, such as ultra-low power, small silicon footprint, reduced communication bandwidth and high efficiency to avoid information loss. The information extraction chain typically involves signal amplification and conditioning, spike detection, and spike sorting to determine the spatial and time firing pattern of each neuron. This thesis first provides a background to the origin and basic electrophysiology of these biopotential signals followed by a thorough review of the relevant state-of-the circuits and systems for facilitating the neural interface. Within this context, novel front-end circuits are presented for achieving resource-constrained biopotential amplification whilst additionally considering the signal dynamics and realistic requirements for effective classification. Specifically, it is shown how a band-limited biopotential amplifier can reduce power requirements without compromising detectability. Furthermore through the development of a novel automatic gain control for neural spike recording, the dynamic range of the signal in subsequent processing blocks can be maintained in multichannel systems. This is particularly effective if now considering systems that no longer requiring independent tuning of amplification gains for each individual channel. This also alleviates the common requirement to over-spec the resolution in data conversion therefore saving power, area and data capacity. Dealing with basic spike detection and feature extraction, a novel circuit for maxima detection is presented for identifying and signalling the onset of spike peaks and troughs. This is then combined with a novel non-linear energy operator (NEO) preprocessor and applied to spike detection. This again contributes to the general theme of achieving a calibration-free multi-channel system that is signal-driven and adaptive. Another original contribution herein includes a spike rate encoder circuit suitable for applications that are not are not affected by providing multi-unit responses. Finally, spike sorting (feature extraction and clustering) is examined. A new method for feature extraction is proposed based on utilising the extrema of the first and second derivatives of the signal. It is shown that this provides an extremely resource-efficient metric than can achieve noise immunity than other methods of comparable complexity. Furthermore, a novel unsupervised clustering method is proposed which adaptively determines the number of clusters and assigns incoming spikes to appropriate cluster on-the-fly. In addition to high accuracy achieved by the combination of these methods for spike sorting, a major advantage is their low-computational complexity that renders them readily implementable in low-power hardware.Open Acces

An implantable micro-system for neural prosthesis control and sensory feedback restoration in amputees

In this work, the prototype of an electronic bi-directional interface between the Peripheral Nervous System (PNS) and a neuro-controlled hand prosthesis is presented. The system is composed of two Integrated Circuits (ICs): a standard CMOS device for neural recording and a High Voltage (HV) CMOS device for neural stimulation. The integrated circuits have been realized in two different 0.35μm CMOS processes available fromAustriaMicroSystem(AMS). The recoding IC incorporates 8 channels each including the analog front-end and the A/D conversion based on a sigma delta architecture. It has a total area of 16.8mm2 and exhibits an overall power consumption of 27.2mW. The neural stimulation IC is able to provide biphasic current pulses to stimulate 8 electrodes independently. A voltage booster generates a 17V voltage supply in order to guarantee the programmed stimulation current even in case of high impedances at the electrode-tissue interface in the order of tens of k­. The stimulation patterns, generated by a 5-bit current DAC, are programmable in terms of amplitude, frequency and pulse width. Due to the huge capacitors of the implemented voltage boosters, the stimulation IC has a wider area of 18.6mm2. In addition, a maximum power consumption of 29mW was measured. Successful in-vivo experiments with rats having a TIME electrode implanted in the sciatic nerve were carried out, showing the capability of recording neural signals in the tens of microvolts, with a global noise of 7μVrms , and to selectively elicit the tibial and plantarmuscles using different active sites of the electrode. In order to get a completely implantable interface, a biocompatible and biostable package was designed. It hosts the developed ICs with the minimal electronics required for their proper operation. The package consists of an alumina tube closed at both extremities by two ceramic caps hermetically sealed on it. Moreover, the two caps serve as substrate for the hermetic feedthroughs to enable the device powering and data exchange with the external digital controller implemented on a Field-Programmable Gate Array (FPGA) board. The package has an outer diameter of 7mm and a total length of 26mm. In addition, a humidity and temperature sensor was also included inside the package to allow future hermeticity and life-time estimation tests. Moreover, a wireless, wearable and non-invasive EEG recording system is proposed in order to improve the control over the artificial limb,by integrating the neural signals recorded from the PNS with those directly acquired from the brain. To first investigate the system requirements, a Component-Off-The-Shelf (COTS) device was designed. It includes a low-power 8- channel acquisition module and a Bluetooth (BT) transceiver to transmit the acquired data to a remote platform. It was designed with the aimof creating a cheap and user-friendly system that can be easily interfaced with the nowadays widely spread smartphones or tablets by means of a mobile-based application. The presented system, validated through in-vivo experiments, allows EEG signals recording at different sample rates and with a maximum bandwidth of 524Hz. It was realized on a 19cm2 custom PCB with a maximum power consumption of 270mW

Dynamic-range analysis and maximization of micropower Gm-C bandpass filters by adaptive biasing

We analyze and present an input gain-varying scheme for maximizing dynamic range in a well-known G[subscript m]-C bandpass filter by both minimizing noise for small input signals, and by achieving balanced swing levels at all filter nodes for large input signals. A micropower bandpass filter suitable for use in cochlear implants and other power-constrained biomedical applications was implemented and tested in subthreshold CMOS. At a center frequency of 1.4 kHz and quality factor of 4, the filter has 70 dB of dynamic range (57 dB maximum SNR, 2.5% total harmonic distortion (THD)) and consumes 2.55 muW of power

Microelectronic Design with Integrated Magnetic and Piezoelectric Structures

This thesis investigates the possibility of integrating the standard CMOS design process with additional microstructures enhancing circuit functionalities. More specifically, the thesis faces the problem of miniaturization of magnetic and piezoelectric devices mostly focused on the application field of EH (Energy Harvesting) systems and ultra-low power and ultra-low voltage systems. It shows all the most critical aspects which have to be taken into account during the design process of miniaturized inductors for PwrSoC (Power System on Chip) or transformers. Furthermore it shows that it is possible to optimize the inductance value and also performances by means of a proper choice of the size of the planar core or choosing a different layout shape such as a serpentine shape in place of the classic toroidal one. A new formula for the correct evaluation of the MPL (Magnetic Path Length) was also introduced. Concerning the piezoelectric counterpart, it is focused on the design and simulation of various MEMS PTs based on a SOI (Silicon on Insulator) structure with AlN (Alluminum Nitride) as active piezoelectric element, in perspective of having a SoC with embedded MEMS devices and circuitry. Furthermore it demonstrates for the first time the use of a PT (Piezoelectric Transformer) for ultra-low voltage EH applications. A new boost oscillator based on a discrete PZT (Lead Zirconate Titanate) PT instead of a MT (Magnetic Transformer) has been modelled and tested on a circuit made up by discrete devices, showing performances comparable to commercial solutions like the LTC3108 from Linear. Furthermore this novel boost oscillator has been designed in a 0.35μm technology by ST Microelectronics, showing better performances as intuitively expected by the developed mathematical model of the entire system

Intrinsic Hardware Evolution on the Transistor Level

This thesis presents a novel approach to the automated synthesis of analog circuits. Evolutionary algorithms are used in conjunction with a fitness evaluation on a dedicated ASIC that serves as the analog substrate for the newly bred candidate solutions. The advantage of evaluating the candidate circuits directly in hardware is twofold. First, it may speed up the evolutionary algorithms, because hardware tests can usually be performed faster than simulations. Second, the evolved circuits are guaranteed to work on a real piece of silicon. The proposed approach is realized as a hardware evolution system consisting of an IBM compatible general purpose computer that hosts the evolutionary algorithm, an FPGA-based mixed signal test board, and the analog substrate. The latter one is designed as a Field Programmable Transistor Array (FPTA) whose programmable transistor cells can be almost freely connected. The transistor cells can be configured to adopt one out of 75 different channel geometries. The chip was produced in a 0.6µm CMOS process and provides ample means for the input and output of analog signals. The configuration is stored in SRAM cells embedded in the programmable transistor cells. The hardware evolution system is used for numerous evolution experiments targeted at a wide variety of different circuit functionalities. These comprise logic gates, Gaussian function circuits, D/A converters, low- and highpass filters, tone discriminators, and comparators. The experimental results are thoroughly analyzed and discussed with respect to related work