A Framework for implementing radiation-tolerant circuits on reconfigurable FPGAs

The outstanding versatility of SRAM-based FPGAs make them the preferred choice for implementing complex customizable circuits. To increase the amount of logic available, manufacturers are using nanometric technologies to boost logic density and reduce prices. However, the use of nanometric scales also makes FPGAs particularly vulnerable to radiation-induced faults, especially because of the increasing amount of configuration memory cells that are necessary to define their functionality. This paper describes a framework for implementing circuits immune to radiation-induced faults, based on a customized Triple Modular Redundancy (TMR) infrastructure and on a detection-and-fix controller. This controller is responsible for the detection of data incoherencies, location of the faulty module and restoration of the original configuration, without affecting the normal operation of the mission logic. A short survey of the most recent data published concerning the impact of radiation-induced faults in FPGAs is presented to support the assumptions underlying our proposed framework. A detailed explanation of the controller functionality is also provided, followed by an experimental case study

Radiation hard FPGA configuration techniques using silicon on sapphire

 Once entirely the domain of space-borne applications, the effects of high energy charged particles on electronics systems is now also a concern for terrestrial devices. Reconfigurable components such as FPGAs are particularly vulnerable to radiation single event effects (SEU) as they carry a large amount of memory within a relatively small amount of circuit area. This thesis presents a Silicon on Insulator (SOI) based configuration memory system in a radiation hard reconfiguration system. The SOI technology used in this particular work is Silicon on Sapphire, where Sapphire is used as the body insulator. A non-volatile storage cell, able to be manufactured in a standard single polysilicon SOI CMOS process with no special layers, is combined with a Schmitt amplifier which result a final structure that exhibits two unique characteristics enhancing its resistance to radiation. Firstly, it is impossible for a radiation induced event to permanently flip the configuration state. Secondly, a partial de-programming resulting in a reduction in the magnitude of the storage cell voltage causes a large change in static current that can be very easily detected using a conventional sense amplifier. A simple current detector of the type used in conventional RAM circuits allows the configuration memory to be set up to exhibit self-correcting, or “auto-scrubbing” behavior. While the combination of SOI EEPROM and Schmitt exhibits high intrinsic resistance to radiation induced errors, it is still possible for a sequence of two particle strikes to cause the configuration value to be lost. Estimates are made of the Soft error Rate (SER) performance of the overall configuration memory structure. A trial layout of a configurable Look Up Table (LUT) is presented as an example of how the SOS EEPROM configuration cell would be deployed in a real system

Self-healing concepts involving fine-grained redundancy for electronic systems

The start of the digital revolution came through the metal-oxide-semiconductor field-effect transistor (MOSFET) in 1959 followed by massive integration onto a silicon die by means of constant down scaling of individual components. Digital systems for certain applications require fault-tolerance against faults caused by temporary or permanent influence. The most widely used technique is triple module redundancy (TMR) in conjunction with a majority voter, which is regarded as a passive fault mitigation strategy. Design by functional resilience has been applied to circuit structures for increased fault-tolerance and towards self-diagnostic triggered self-healing. The focus of this thesis is therefore to develop new design strategies for fault detection and mitigation within transistor, gate and cell design levels. The research described in this thesis makes three contributions. The first contribution is based on adding fine-grained transistor level redundancy to logic gates in order to accomplish stuck-at fault-tolerance. The objective is to realise maximum fault-masking for a logic gate with minimal added redundant transistors. In the case of non-maskable stuck-at faults, the gate structure generates an intrinsic indication signal that is suitable for autonomous self-healing functions. As a result, logic circuitry utilising this design is now able to differentiate between gate faults and faults occurring in inter-gate connections. This distinction between fault-types can then be used for triggering selective self-healing responses. The second contribution is a logic matrix element which applies the three core redundancy concepts of spatial- temporal- and data-redundancy. This logic structure is composed of quad-modular redundant structures and is capable of selective fault-masking and localisation depending of fault-type at the cell level, which is referred to as a spatiotemporal quadded logic cell (QLC) structure. This QLC structure has the capability of cellular self-healing. Through the combination of fault-tolerant and masking logic features the QLC is designed with a fault-behaviour that is equal to existing quadded logic designs using only 33.3% of the equivalent transistor resources. The inherent self-diagnosing feature of QLC is capable of identifying individual faulty cells and can trigger self-healing features. The final contribution is focused on the conversion of finite state machines (FSM) into memory to achieve better state transition timing, minimal memory utilisation and fault protection compared to common FSM designs. A novel implementation based on content-addressable type memory (CAM) is used to achieve this. The FSM is further enhanced by creating the design out of logic gates of the first contribution by achieving stuck-at fault resilience. Applying cross-data parity checking, the FSM becomes equipped with single bit fault detection and correction