Dynamic Energy Management for Chip Multi-processors under Performance Constraints

We introduce a novel algorithm for dynamic energy management (DEM) under performance constraints in chip multi-processors (CMPs). Using the novel concept of delayed instructions count, performance loss estimations are calculated at the end of each control period for each core. In addition, a Kalman filtering based approach is employed to predict workload in the next control period for which voltage-frequency pairs must be selected. This selection is done with a novel dynamic voltage and frequency scaling (DVFS) algorithm whose objective is to reduce energy consumption but without degrading performance beyond the user set threshold. Using our customized Sniper based CMP system simulation framework, we demonstrate the effectiveness of the proposed algorithm for a variety of benchmarks for 16 core and 64 core network-on-chip based CMP architectures. Simulation results show consistent energy savings across the board. We present our work as an investigation of the tradeoff between the achievable energy reduction via DVFS when predictions are done using the effective Kalman filter for different performance penalty thresholds

DeSyRe: on-Demand System Reliability

The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. To make matters worse, power density is becoming a significant limiting factor in SoC design, in general. In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce excessive overheads in future systems. Moreover, attempting to design and manufacture a totally defect and fault-free system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the system performance and power consumption. In this context, DeSyRe delivers a new generation of systems that are reliable by design at well-balanced power, performance, and design costs. In our attempt to reduce the overheads of fault-tolerance, only a small fraction of the chip is built to be fault-free. This fault-free part is then employed to manage the remaining fault-prone resources of the SoC. The DeSyRe framework is applied to two medical systems with high safety requirements (measured using the IEC 61508 functional safety standard) and tight power and performance constraints

A multiprocessor based packet-switch: performance analysis of the communication infrastructure

The intra-chip communication infrastructures are receiving always more attention since they are becoming a crucial part in the development of current SoCs. Due to the high availability of pre-characterized hard-IP, the complexity of the design is moving toward global interconnections which are introducing always more constraints at each technology node. Power consumption, timing closure, bandwidth requirements, time to market, are some of the factors that are leading to the proposal of new solutions for next generation multi-million SoCs. The need of high programmable systems and the high gate-count availability is moving always more attention on multiprocessors systems (MP-SoC) and so an adequate solution must be found for the communication infrastructure. One of the most promising technologies is the Network-On-Chip (NoC) architecture, which seems to better fit with the new demanding complexity of such systems. Before starting to develop new solutions, it is crucial to fully understand if and when current bus architectures introduce strong limitations in the development of high speed systems. This article describes a case study of a multiprocessor based ethernet packet-switch application with a shared-bus communication infrastructure. This system aims to depict all the bottlenecks which a shared-bus introduces under heavy load. What emerges from this analysis is that, as expected, a shared-bus is not scalable and it strongly limits whole system performances. These results strengthen the hypothesis that new communication architectures (like the NoC) must be found

The Chameleon Architecture for Streaming DSP Applications

We focus on architectures for streaming DSP applications such as wireless baseband processing and image processing. We aim at a single generic architecture that is capable of dealing with different DSP applications. This architecture has to be energy efficient and fault tolerant. We introduce a heterogeneous tiled architecture and present the details of a domain-specific reconfigurable tile processor called Montium. This reconfigurable processor has a small footprint (1.8 mm$^2$ in a 130 nm process), is power efficient and exploits the locality of reference principle. Reconfiguring the device is very fast, for example, loading the coefficients for a 200 tap FIR filter is done within 80 clock cycles. The tiles on the tiled architecture are connected to a Network-on-Chip (NoC) via a network interface (NI). Two NoCs have been developed: a packet-switched and a circuit-switched version. Both provide two types of services: guaranteed throughput (GT) and best effort (BE). For both NoCs estimates of power consumption are presented. The NI synchronizes data transfers, configures and starts/stops the tile processor. For dynamically mapping applications onto the tiled architecture, we introduce a run-time mapping tool

Performance Evaluation of Centralized Reconfigurable Transmitting Power Scheme in Wireless Network-on-chip

Network-on-chip (NoC) is an on-chip communication network that allows parallel communication among all cores to improve inter-core performance. Wireless NoC (WiNoC) introduces long-range and high bandwidth radio frequency (RF) interconnects that can possibly reduce the multi-hop communication of the planar metal interconnects in conventional NoC platforms. In WiNoC, RF transceivers account for a significant power consumption, particularly its transmitter, out of its total communication energy. This paper evaluates the energy and latency performance of a closed loop power management mechanism which enables transmitting power reconfiguration in WiNoC based on number of erroneous received packets. The scheme achieves significant energy savings with limited performance degradation and insignificant impact on throughput

Meeting report : NERC Integrated Environmental Modelling Workshop : held at the British Geological Survey, Keyworth, 4-5th February

This report describes the results of the NERC Integrated Environmental Modelling (IEM) workshop that was held at BGS Keyworth on the 4th to 5th February, 2014. The meeting brought together some 35 scientists from the NERC Science Office and five NERC centres and surveys. The workshop builds on previous meetings which have been convened over a number of years; such as the International summit on Integrated Environmental Modelling, Washington (2010), the AGU fall meeting, San Francisco (2009), and the international congress on Environmental Modelling and Software (2010). From these meetings it was recognised that there were many communities involved in developing IEM and that the two main groups of the US and Europe needed to work together to create an open community for all. Out of these meetings it was clear that there was a need to; provide accessible linkable components, to address uncertainty, to professionalise the development of integrated models, to engage with the user community (particularly decision and policy-makers) and to develop a community of practise to aid the development and uptake of IEM. The aim of this meeting was to: Develop a strategy for Integrated Environmental Modelling (IEM) within NERC Develop an Integrated Environmental Modelling Methodology that can be easily adopted both inside and outside NERC Establish several exemplar projects that are cross-cutting (institutional and discipline) and also deliver the key goals of IEM and the new NERC strategy The outcomes from the Washington meeting in 2010 have been considered and further developed. From this, the proposed NERC IEM strategy has been broken down into 4 key areas which formed the topics for each of the breakout groups and are: - 1. The premise that eventually all models will at some point in their life-cycle need to be linked to other models. What needs to be done to enable this to happen? 2. To encourage the development of modelling platforms. What needs to be done to enable this to happen? 3. To assess and quantify uncertainty arising from integrated modelling. What needs to be done to enable this to happen? 4. To develop specific exemplar projects. How should this be done within NERC and with NERC's partners? The report outlines the strategy and vision for Integrated Environmental Modelling in NERC and then gives a description of the main findings from each of the 4 main topics areas addressed within the NERC IEM worksho