Photon Counting OTDR : Advantages and Limitations

We give detailed insight into photon counting OTDR (nu-OTDR) operation, ranging from Geiger mode operation of avalanche photodiodes (APD), analysis of different APD bias schemes, to the discussion of OTDR perspectives. Our results demonstrate that an InGaAs/InP APD based nu-OTDR has the potential of outperforming the dynamic range of a conventional state-of-the-art OTDR by 10 dB as well as the 2-point resolution by a factor of 20. Considering the trace acquisition speed of nu-OTDRs, we find that a combination of rapid gating for high photon flux and free running mode for low photon flux is the most efficient solution. Concerning dead zones, our results are less promising. Without additional measures, e.g. an optical shutter, the photon counting approach is not competitive.Comment: 12 pages, 13 figures, accepted for publication by IEEE Journal of Lightwave Technolog

The Octopus switch

This chapter1 discusses the interconnection architecture of the Mobile Digital Companion. The approach to build a low-power handheld multimedia computer presented here is to have autonomous, reconfigurable modules such as network, video and audio devices, interconnected by a switch rather than by a bus, and to offload as much as work as possible from the CPU to programmable modules placed in the data streams. Thus, communication between components is not broadcast over a bus but delivered exactly where it is needed, work is carried out where the data passes through, bypassing the memory. The amount of buffering is minimised, and if it is required at all, it is placed right on the data path, where it is needed. A reconfigurable internal communication network switch called Octopus exploits locality of reference and eliminates wasteful data copies. The switch is implemented as a simplified ATM switch and provides Quality of Service guarantees and enough bandwidth for multimedia applications. We have built a testbed of the architecture, of which we will present performance and energy consumption characteristics

Characterizing mixed mode oscillations shaped by noise and bifurcation structure

Many neuronal systems and models display a certain class of mixed mode oscillations (MMOs) consisting of periods of small amplitude oscillations interspersed with spikes. Various models with different underlying mechanisms have been proposed to generate this type of behavior. Stochastic versions of these models can produce similarly looking time series, often with noise-driven mechanisms different from those of the deterministic models. We present a suite of measures which, when applied to the time series, serves to distinguish models and classify routes to producing MMOs, such as noise-induced oscillations or delay bifurcation. By focusing on the subthreshold oscillations, we analyze the interspike interval density, trends in the amplitude and a coherence measure. We develop these measures on a biophysical model for stellate cells and a phenomenological FitzHugh-Nagumo-type model and apply them on related models. The analysis highlights the influence of model parameters and reset and return mechanisms in the context of a novel approach using noise level to distinguish model types and MMO mechanisms. Ultimately, we indicate how the suite of measures can be applied to experimental time series to reveal the underlying dynamical structure, while exploiting either the intrinsic noise of the system or tunable extrinsic noise.Comment: 22 page

Semiconductor optical amplifiers: performance and applications in optical packet switching [Invited]

Semiconductor optical amplifiers (SOAs) are a versatile core technology and the basis for the implementation of a number of key functionalities central to the evolution of highly wavelength-agile all-optical networks. We present an overview of the state of the art of SOAs and summarize a range of applications such as power boosters, preamplifiers, optical linear (gain-clamped) amplifiers, optical gates, and modules based on the hybrid integration of SOAs to yield high-level functionalities such as all-optical wavelength converters/regenerators and small space switching matrices. Their use in a number of proposed optical packet switching situations is also highlighted

A low-power, high-performance speech recognition accelerator

© 2019 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Automatic Speech Recognition (ASR) is becoming increasingly ubiquitous, especially in the mobile segment. Fast and accurate ASR comes at high energy cost, not being affordable for the tiny power-budgeted mobile devices. Hardware acceleration reduces energy-consumption of ASR systems, while delivering high-performance. In this paper, we present an accelerator for largevocabulary, speaker-independent, continuous speech-recognition. It focuses on the Viterbi search algorithm representing the main bottleneck in an ASR system. The proposed design consists of innovative techniques to improve the memory subsystem, since memory is the main bottleneck for performance and power in these accelerators' design. It includes a prefetching scheme tailored to the needs of ASR systems that hides main memory latency for a large fraction of the memory accesses, negligibly impacting area. Additionally, we introduce a novel bandwidth-saving technique that removes off-chip memory accesses by 20 percent. Finally, we present a power saving technique that significantly reduces the leakage power of the accelerators scratchpad memories, providing between 8.5 and 29.2 percent reduction in entire power dissipation. Overall, the proposed design outperforms implementations running on the CPU by orders of magnitude, and achieves speedups between 1.7x and 5.9x for different speech decoders over a highly optimized CUDA implementation running on Geforce-GTX-980 GPU, while reducing the energy by 123-454x.Peer ReviewedPostprint (author's final draft

Analysis and design of a modular multilevel converter with trapezoidal modulation for medium and high voltage DC-DC transformers

Conventional dual active bridge topologies provide galvanic isolation and soft-switching over a reasonable operating range without dedicated resonant circuits. However, scaling the two-level dual active bridge to higher dc voltage levels is impeded by several challenges among which the high dv/dt stress on the coupling transformer insulation. Gating and thermal characteristics of series switch arrays add to the limitations. To avoid the use of standard bulky modular multilevel bridges, this paper analyzes an alternative modulation technique where staircase approximated trapezoidal voltage waveforms are produced; thus alleviating developed dv/dt stresses. Modular design is realized by the utilization of half-bridge chopper cells. Therefore, the analyzed converter is a modular multi-level converter operated in a new mode with no common-mode dc arm currents as well as reduced capacitor size, hence reduced cell footprint. Suitable switching patterns are developed and various design and operation aspects are studied. Soft switching characteristics will be shown to be comparable to those of the two-level dual active bridge. Experimental results from a scaled test rig validate the presented concept

Nanowire Volatile RAM as an Alternative to SRAM

Maintaining benefits of CMOS technology scaling is becoming challenging due to increased manufacturing complexities and unwanted passive power dissipations. This is particularly challenging in SRAM, where manufacturing precision and leakage power control are critical issues. To alleviate some of these challenges a novel non-volatile memory alternative to SRAM was proposed called nanowire volatile RAM (NWRAM). Due to NWRAMs regular grid based layout and innovative circuit style, manufacturing complexity is reduced and at the same time considerable benefits are attained in terms of performance and leakage power reduction. In this paper, we elaborate more on NWRAM circuit aspects and manufacturability, and quantify benefits at 16nm technology node through simulation against state-of-the-art 6T-SRAM and gridded 8T-SRAM designs. Our results show the 10T-NWRAM to be 2x faster and 35x better in terms of leakage when compared to high performance gridded 8T-SRAM design