A Software Defined Radio Platform with Direct Conversion: SOPRANO

A new software defined radio platform with multiport-based direct conversion is proposed, named SOPRANO (Software Programmable and Hardware Reconfigurable Architecture for Network). The main features of SOPRANO are a high-level design methodology for digital circuits, a new mixer-less direct conversion method, and software algorithms for multi-band and multi-mode operation. We built the first prototype SOPRANO 1.0, which was able to receive PSK and QAM signals with two different carrier frequencies at 2.45 GHz and 5.25 GHz by changing signal processing software

A low-complexity feed-forward I/Q imbalance compensation algorithm

This paper presents a low-complexity adaptive feed- forward I/Q imbalance compensation algorithm. The feed-forward so- lution has guaranteed stability. Due to its blind nature the algorithm is easily incorporated into an existing receiver design. The algorithm uses three estimators to obtain the necessary parameters for the I/Q imbal- ance compensation structure. The algorithm complexity is low due to 1-bit quantization in the estimators. Simulations show that the compen- sation algorithm is able to attain an image-rejection ratio (IRR) of up to 65 [dB] under various imbalance conditions

RF receiver design using the direct conversion approach at 5.8 GHz band based on IEEE 802.11a standard

This thesis presents the development and analysis of a radio frequency (RF) front-end direct conversion receiver at 5.725 – 5.825 GHz where IEEE 802.11a standard is used as performance test. The RF receiver is designed based on the commercialized products (off-the-shelf) where it focuses on the system design tradeoff, rather than circuit design tradeoff. The RF receiver has been designed with the selected architecture where it is consist of low noise amplifier (LNA), radio frequency amplifier (RFA), power divider and two bandpass filters. The modeled RF receiver has been analyzed by using Advanced Design System (ADS) 2005A software for system characteristic and performance test. From the simulation, minimum sensitivity is -91 dBm at data rate 6 Mbps and -74 dBm at data rate 54 Mbps where it is comply with the IEEE 802.11a standard. The RF receiver prototype has been measured and this system produces has gain of 39 dB which is higher than the reviewed of 37.5 dB. The noise figure of this work is measured at 1.30 dB, which is better than the reviewed work at 4.6 dB. The nonlinearity characteristic such as power at 1dB compression point (P1dB) and third order intercept point (IP3) is observed. From the measurement, the RF receiver will drop 1 dB when input power (Pin) is injected above -27 dBm then it caused output power (Pout) start saturated. The third output intercept point (OIP3) and third input intercept point (IIP3) is at around 15 dBm and -24.50 dBm respectively. The RF receiver system characteristic such as sensitivity meet the standard requirement of IEEE 802.11a standard for wireless local area network (WLAN) bridge system.

Frequency Estimation in OFDM Direct-Conversion Receivers Using a Repeated Preamble

This paper investigates the problem of carrier frequency offset (CFO) recovery in an OFDM receiver affected by frequency-selective in-phase/quadrature (I/Q) imbalances. The analysis is based on maximum-likelihood (ML) methods and relies on the transmission of a training preamble with a repetitive structure in the time domain. After assessing the accuracy of the conventional ML (CML) scheme in a scenario characterized by I/Q impairments, we review the joint ML (JML) estimator of all unknown parameters and evaluate its theoretical performance. In order to improve the estimation accuracy, we also present a novel CFO recovery method that exploits some side-information about the signal-to-interference ratio. It turns out that both CML and JML can be derived from this scheme by properly adjusting the value of a design parameter. The accuracy of the investigated methods are compared with the relevant Cramer-Rao bound. Our results can be used to check whether conventional CFO recovery algorithms can work properly or not in the presence of I/Q imbalances and also to evaluate the potential gain attainable by more sophisticated schemes

Periodic Preamble-Based Frequency Recovery in OFDM Receivers Plagued by I/Q Imbalance

The direct conversion receiver (DCR) architecture has received much attention in the last few years as an effective means to obtain user terminals with reduced cost, size, and power consumption. A major drawback of a DCR device is the possible insertion of I/Q imbalances in the demodulated signal, which can seriously degrade the performance of conventional synchronization algorithms. In this paper, we investigate the problem of carrier frequency offset (CFO) recovery in an OFDM receiver equipped with a DCR front-end. Our approach is based on maximum likelihood (ML) arguments and aims at jointly estimating the CFO, the useful signal component, and its mirror image. In doing so, we exploit knowledge of the pilot symbols transmitted within a conventional repeated training preamble appended in front of each data packet. Since the exact ML solution turns out to be too complex for practical purposes, we propose two alternative schemes which can provide nearly optimal performance with substantial computational saving. One of them provides the CFO in closed-form, thereby avoiding any grid-search procedure. The accuracy of the proposed methods is assessed in a scenario compliant with the 802.11a WLAN standard. Compared with existing solutions, the novel schemes achieve improved performance at the price of a tolerable increase of the processing load

Design and Optimization of a Direct-Conversion Double-Balanced Mixer for RF Receiver Front-End

Differential implementation is becoming highly favoured in RFIC (radio frequency integrated circuit) design, notably its high immunity to common-mode noises, acceptable rejection of parasitic coupling, and increased dynamic range. One specific RF front-end building block that is usually designed as a differential circuit is the mixer.  This technical paper presents a study of a differential mixer, notably the double-balanced mixer implemented on a direct-conversion architecture in a standard 90nm CMOS (complementary metal-oxide semiconductor) process.  Operating frequency is set at 5GHz, which is a typical frequency for RF (radio frequency) receiver.   Impedance matching was essential to fully optimize the mixer design.  The direct-conversion double-balance mixer design eventually achieved conversion gain of 11.463dB and noise figure of 16.529dB, comparable to mixer designs from past research and studies

Baseband Noise Suppression in Ofdm Using Kalman Filter

As the technology is advances the reduced size of hardware gives rise to an additive 1/f baseband noise. This additive 1/f noise is a system noise generated due to miniaturization of hardware and affects the lower frequencies. Though 1/f noise does not show much effect in wide band channels because of its nature to affect only certain frequencies, 1/f noise becomes a prominent in OFDM communication systems where narrow band channels are used. in this thesis, I study the effects of 1/f noise on the OFDM systems and implement algorithms for estimation and suppression of the noise using Kalman filter. Suppression of the noise is achieved by subtracting the estimated noise from the received noise. I show that the performance of the system is considerably improved by applying the 1/f noise suppression

24GHz CMOS direct downconversion receiver front-end and VCO design

Because of advancements in RF CMOS circuits, devices, and passive elements in the last decade, it has become possible to develop a RF system-on-chip (SoC) that integrates RF, analog and digital circuits completely. Direct downconversion, or zero-IF downconversion architecture, shows an advantage over traditional superheterodyne architectures, because it eliminates the image rejection filter and IF filter, and employs only one local oscillator (LO), which reduces the receiver size and power dissipation significantly. For this reason, direct downconversion has drawn more and more attention recently in various wireless applications. However, it also presents some design challenges like flicker noise, DC offsets, even-order distortion, and I/Q mismatches. In this work, a thorough noise analysis and a comprehensive study of the noise mechanism of the low noise amplifier of CMOS direct downconversion receivers (DCR) is given. Also addressed is the design of a cross-coupled LC voltage-controlled oscillator (VCO). For the low noise amplifier, which presents major noise contribution to the DCR front-end, an optimization technique which employs both a parallel capacitance and an inter-stage inductor is proposed. The addition of this capacitance helps keep the active device relatively small, and the analysis on the effects of the inter-stage inductor shows that it helps boost gain of the LNA at the desired operation frequency of 2.4GHz, and offers a lower noise figure. In order to achieve direct downconversion, both a passive switching mixer and an active double-balanced mixer are presented. The passive switching mixer helps solve the problem of flicker noise, but suffers power loss, while the double-balanced architecture helps relieve the problems of DC offset and second-order distortion. The last part of this presentation is about a partially tunable CMOS LC-VCO which achieves good phase noise performance at the cost of smaller tuning range. It uses on-chip spiral inductors and junction varactors in the resonant LC-tank. The presented building blocks can be used for a low-power, low-voltage DCR front-end for 802.11b/g applications. It is concluded that direct downconversion architecture can find its use in low-power, low-cost 802.11b and Bluetooth applications should the circuit design make use of the optimization techniques addressed in this work

An adaptive algorithm for direct conversion receivers: Architecture and performance analysis

Master'sMASTER OF ENGINEERIN