On evolution of CMOS image sensors

CMOS Image Sensors have become the principal technology in majority of digital cameras. They started replacing the film and Charge Coupled Devices in the last decade with the promise of lower cost, lower power requirement, higher integration and the potential of focal plane processing. However, the principal factor behind their success has been the ability to utilise the shrinkage in CMOS technology to make smaller pixels, and thereby have more resolution without increasing the cost. With the market of image sensors exploding courtesy their inte- gration with communication and computation devices, technology developers improved the CMOS processes to have better optical performance. Nevertheless, the promises of focal plane processing as well as on-chip integration have not been fulfilled. The market is still being pushed by the desire of having higher number of pixels and better image quality, however, differentiation is being difficult for any image sensor manufacturer. In the paper, we will explore potential disruptive growth directions for CMOS Image sensors and ways to achieve the same

CMOS image sensor with bi-directional column sensor

CMOS image sensors have been around since the 1960\u27s. However due to poor light sensitivity and poor signal-to-noise ratios (SNR) the architecture was not popular. Since then many improvements have been made to the architecture, making camera designs that use CMOS imagers more prevalent. Much of the improvement in SNR has been due to fixed-pattern noise reduction. Correlated double sampling (CDS) is a popular technique to reduce the effects of this source of noise. The circuitry required to implement CDS can be complex and hinders other areas of an image sensor performance in some schemes. This thesis proposes a new technique that attenuates noise due to DC offset without the use of CDS. Beginning with a standard three transistor-per-pixel architecture, this thesis builds on previous CMOS image sensor designs and creates a new bi-directional amplifier architecture that eliminates DC offset due to transistor mismatch without the use of CDS. The architecture uses a single differential amplifier to both reset and readout the pixel. Simulations show that SNR range of the proposed column sensor is 48.71 - 44.63 dB, whereas an Active Column Sensor without CDS has an SNR of 31.88 - 28.78 dB under the same conditions. Using the proposed column sensor, a layout (TSMC 0.35um) for a small 4X4 pixel image sensor was designed and prototyped which proves that the bi-directional amplifier can be used as a column sensor. The proposed prototype shows the viability of the architecture for a future production camera. The simulated result for the image sensor show that it can be reset in 200 ns read out in 3.4us and has an overall size of 107.9X118.1 um2

High Speed Camera Chip

abstract: The market for high speed camera chips, or image sensors, has experienced rapid growth over the past decades owing to its broad application space in security, biomedical equipment, and mobile devices. CMOS (complementary metal-oxide-semiconductor) technology has significantly improved the performance of the high speed camera chip by enabling the monolithic integration of pixel circuits and on-chip analog-to-digital conversion. However, for low light intensity applications, many CMOS image sensors have a sub-optimum dynamic range, particularly in high speed operation. Thus the requirements for a sensor to have a high frame rate and high fill factor is attracting more attention. Another drawback for the high speed camera chip is its high power demands due to its high operating frequency. Therefore, a CMOS image sensor with high frame rate, high fill factor, high voltage range and low power is difficult to realize. This thesis presents the design of pixel circuit, the pixel array and column readout chain for a high speed camera chip. An integrated PN (positive-negative) junction photodiode and an accompanying ten transistor pixel circuit are implemented using a 0.18 µm CMOS technology. Multiple methods are applied to minimize the subthreshold currents, which is critical for low light detection. A layout sharing technique is used to increase the fill factor to 64.63%. Four programmable gain amplifiers (PGAs) and 10-bit pipeline analog-to-digital converters (ADCs) are added to complete on-chip analog to digital conversion. The simulation results of extracted circuit indicate ENOB (effective number of bits) is greater than 8 bits with FoM (figures of merit) =0.789. The minimum detectable voltage level is determined to be 470μV based on noise analysis. The total power consumption of PGA and ADC is 8.2mW for each conversion. The whole camera chip reaches 10508 frames per second (fps) at full resolution with 3.1mm x 3.4mm area.Dissertation/ThesisMasters Thesis Electrical Engineering 201

A Review on Digital Pixel Sensors

Digital pixel sensor (DPS) has evolved as a pivotal component in modern imaging systems and has the potential to revolutionize various fields such as medical imaging, astronomy, surveillance, IoT devices, etc. Compared to analog pixel sensors, the DPS offers high speed and good image quality. However, the introduced intrinsic complexity within each pixel, primarily attributed to the accommodation of the ADC circuit, engenders a substantial increase in the pixel pitch. Unfortunately, such a pronounced escalation in pixel pitch drastically undermines the feasibility of achieving high-density integration, which is an obstacle that significantly narrows down the field of potential applications. Nonetheless, designing compact conversion circuits along with strategic integration of 3D architectural paradigms can be a potential remedy to the prevailing situation. This review article presents a comprehensive overview of the vast area of DPS technology. The operating principles, advantages, and challenges of different types of DPS circuits have been analyzed. We categorize the schemes into several categories based on ADC operation. A comparative study based on different performance metrics has also been showcased for a well-rounded understanding

Gain and Offset Error Correction for CMOS Image Sensor Using Delta-Sigma Modulation

A delta-sigma modulation analog-to-digital converter (ADC) has many benefits over the use of a pipeline ADC in a CMOS image sensor. These benefits include lower power, noise reduction, ease of maximizing the input range, and simpler signal routing for large arrays. Multiple delta-sigma modulation ADCs are required in a CMOS image sensor, one for each pixel column. Any voltage threshold mismatch between ADCs will introduce gain and offset errors in the ADC\u27s transfer function. These errors will lead to fixed-pattern noise. Correcting gain and offset error for every ADCs in the image sensor will require a complex digital signal processor. This thesis presents techniques to minimize the effects of gain and offset errors in delta-sigma modulation ADCs for CMOS image sensors

Recent Design Development in Molecular Imaging for Breast Cancer Detection Using Nanometer CMOS Based Sensors

As one of the key clinical imaging methods, the computed X-ray tomography can be further improved using new nanometer CMOS sensors. This will enhance the current technique's ability in terms of cancer detection size, position, and detection accuracy on the anatomical structures. The current paper reviewed designs of SOI-based CMOS sensors and their architectural design in mammography systems. Based on the existing experimental results, using the SOI technology can provide a low-noise (SNR around 87.8 db) and high-gain (30 v/v) CMOS imager. It is also expected that, together with the fast data acquisition designs, the new type of imagers may play important roles in the near-future high-dimensional images in additional to today's 2D imagers

Bits from Photons: Oversampled Image Acquisition Using Binary Poisson Statistics

We study a new image sensor that is reminiscent of traditional photographic film. Each pixel in the sensor has a binary response, giving only a one-bit quantized measurement of the local light intensity. To analyze its performance, we formulate the oversampled binary sensing scheme as a parameter estimation problem based on quantized Poisson statistics. We show that, with a single-photon quantization threshold and large oversampling factors, the Cram\'er-Rao lower bound (CRLB) of the estimation variance approaches that of an ideal unquantized sensor, that is, as if there were no quantization in the sensor measurements. Furthermore, the CRLB is shown to be asymptotically achievable by the maximum likelihood estimator (MLE). By showing that the log-likelihood function of our problem is concave, we guarantee the global optimality of iterative algorithms in finding the MLE. Numerical results on both synthetic data and images taken by a prototype sensor verify our theoretical analysis and demonstrate the effectiveness of our image reconstruction algorithm. They also suggest the potential application of the oversampled binary sensing scheme in high dynamic range photography

Analysis and design of a wide dynamic range pulse-frequency modulation CMOS image sensor

Complementary Metal-Oxide Semiconductor (CMOS) image sensor is the dominant electronic imaging device in many application fields, including the mobile or portable devices, teleconference cameras, surveillance and medical imaging sensors. Wide dynamic range (WDR) imaging is of interest particular, demonstrating a large-contrast imaging range of the sensor. As of today, different approaches have been presented to provide solutions for this purpose, but there exists various trade-offs among these designs, which limit the number of applications. A pulse-frequency modulation (PFM) pixel offers the possibility to outperform existing designs in WDR imaging applications, however issues such as uniformity and cost have to be carefully handled to make it practical for different purposes. In addition, a complete evaluation of the sensor performance has to be executed prior to fabrication in silicon technology. A thorough investigation of WDR image sensor based on the PFM pixel is performed in this thesis. Starting with the analysis, modeling, and measurements of a PFM pixel, the details of every particular circuit operation are presented. The causes of dynamic range (DR) limitations and signal nonlinearity are identified, and noise measurement is also performed, to guide future design strategies. We present the design of an innovative double-delta compensating (DDC) technique which increases the sensor uniformity as well as DR. This technique achieves performance optimization of the PFM pixel with a minimal cost an improved linearity, and is carefully simulated to demonstrate its feasibility. A quad-sampling technique is also presented with the cooperation of pixel and column circuits to generate a WDR image sensor with a reduced cost for the pixel. This method, which is verified through the field-programmable gate array (FPGA) implementation, saves considerable area in the pixel and employs the maximal DR that a PFM pixel provides. A complete WDR image sensor structure is proposed to evaluate the performance and feasibility of fabrication in silicon technology. The plans of future work and possible improvements are also presented