Experimental study of artificial neural networks using a digital memristor simulator

© 2018 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.This paper presents a fully digital implementation of a memristor hardware simulator, as the core of an emulator, based on a behavioral model of voltage-controlled threshold-type bipolar memristors. Compared to other analog solutions, the proposed digital design is compact, easily reconfigurable, demonstrates very good matching with the mathematical model on which it is based, and complies with all the required features for memristor emulators. We validated its functionality using Altera Quartus II and ModelSim tools targeting low-cost yet powerful field programmable gate array (FPGA) families. We tested its suitability for complex memristive circuits as well as its synapse functioning in artificial neural networks (ANNs), implementing examples of associative memory and unsupervised learning of spatio-temporal correlations in parallel input streams using a simplified STDP. We provide the full circuit schematics of all our digital circuit designs and comment on the required hardware resources and their scaling trends, thus presenting a design framework for applications based on our hardware simulator.Peer ReviewedPostprint (author's final draft

A Ringamp-Assisted, Output Capacitor-less Analog CMOS Low-Dropout Voltage Regulator

Continued advancements in state-of-the-art integrated circuits have furthered trends toward higher computational performance and increased functionality within smaller circuit area footprints, all while improving power efficiencies to meet the demands of mobile and battery-powered applications. A significant portion of these advancements have been enabled by continued scaling of CMOS technology into smaller process node sizes, facilitating faster digital systems and power optimized computation. However, this scaling has degraded classic analog amplifying circuit structures with reduced voltage headroom and lower device output resistance; and thus, lower available intrinsic gain. This work investigates these trends and their impact for fine-grain Low-Dropout (LDO) Voltage Regulators, leading to a presented design methodology and implementation of a state-of-the-art Ringamp-Assisted, Output Capacitor-less Analog CMOS LDO Voltage Regulator capable of both power scaling and process node scaling for general SoC applications

1.2 Racing Down the Slopes of Moore's Law

Since its inception, Moore's Law has been the driving force for IC design. Although during the first decade, 'everything' seemed to be better, however, we lost the scaling of processor clock speed and RF transistor speed, and now it looks as if power efficiency of digital gates will stall. What remains is scaling in transistor count and cost-per-function, thanks to 3D integration.Thus, this is an excellent moment to reconsider how we design for analog and digital signal processing. The higher the required signal-to-noise ratio (SNR), the more power-efficient digital signal processing is compared to analog. Pure analog processing remains more efficient only for ~ 30 dB SNR or less. In the case of digital processing, the conversion from analog to digital should therefore be made as early in the signal chain as possible. Thanks to the figure-of-merit race, analog-to-digital converters (ADCs) have experienced a tremendous win in power efficiency. However, these ADCs require a large input voltage swing while the input signals to be converted, from an antenna or sensor interface, are usually much smaller. Therefore, RF and analog front-ends are needed, which consume much more power than the ADCs to be driven.Let us re-think these analog front-ends. Can we still efficiently design these front-ends in future CMOS? Do we need so much linear amplification? Do we need active linear circuits at all? Can we not use 'digital' components to replace the analog front-ends and ADCs? This paper aims to look at digital and analog processing trends from technology and design fundamentals points of view. We will first zoom out on asymptotic trends in technology scaling and try to identify future design opportunities and challenges. For circuit design, fundamental limits linking power, speed, and accuracy will be reviewed to gain insight into the implications of how we design circuits the way we currently do. This paper aims to create awareness and gives a new vision of designing analog circuits.</p

Design of digital electricity meter

Common Electricity meters, which are currently used in houses, shops and some factories are bulky expensive and inaccurate. Such features are incompatible with modern technological trends of miniaturization accuracy and neat devices. This project presents the design and the model of a low cost digital energy meter to overcome the short comings of the present meters. It is anticipated that a new neat design based on integrated circuit technology employing digital measurement techniques will have a great impact on electricity meters locally and worldwide. With a data storage capability and some form of processing, it can provide the consumers with vital information on the trend of their energy consumption. Such information will assist them in rationalizing their consumption. Intelligent energy meters may be seen as most suitable and efficient way to facilitate easy solutions to the problem of rational consumption

Trends and challenges in VLSI technology scaling towards 100 nm

Summary form only given. Moore's Law drives VLSI technology to continuous increases in transistor densities and higher clock frequencies. This tutorial will review the trends in VLSI technology scaling in the last few years and discuss the challenges facing process and circuit engineers in the 100nm generation and beyond. The first focus area is the process technology, including transistor scaling trends and research activities for the 100nm technology node and beyond. The transistor leakage and interconnect RC delays will continue to increase. The tutorial will review new circuit design techniques for emerging process technologies, including dual Vt transistors and silicon-on-insulator. It will also cover circuit and layout techniques to reduce clock distribution skew and jitter, model and reduce transistor leakage and improve the electrical performance of flip-chip packages. Finally, the tutorial will review the test challenges for the 100nm technology node due to increased clock frequency and power consumption (both active and passive) and present several potential solution

Systematic Comparison of HF CMOS Transconductors

Transconductors are commonly used as active elements in high-frequency (HF) filters, amplifiers, mixers, and oscillators. This paper reviews transconductor design by focusing on the V-I kernel that determines the key transconductor properties. Based on bandwidth considerations, simple V-I kernels with few or no internal nodes are preferred. In a systematic way, virtually all simple kernels published in literature are generated. This is done in two steps: 1) basic 3-terminal transconductors are covered and 2) then five different techniques to combine two of them in a composite V-I kernel. In order to compare transconductors in a fair way, a normalized signal-to-noise ratio (NSNR) is defined. The basic V-I kernels and the five classes of composite V-I kernels are then compared, leading to insight in the key mechanisms that affect NSNR. Symbolic equations are derived to estimate NSNR, while simulations with more advanced MOSFET models verify the results. The results show a strong tradeoff between NSNR and transconductance tuning range. Resistively generated MOSFETs render the best NSNR results and are robust for future technology developments

Analog Circuits in Ultra-Deep-Submicron CMOS

Modern and future ultra-deep-submicron (UDSM) technologies introduce several new problems in analog design. Nonlinear output conductance in combination with reduced voltage gain pose limits in linearity of (feedback) circuits. Gate-leakage mismatch exceeds conventional matching tolerances. Increasing area does not improve matching any more, except if higher power consumption is accepted or if active cancellation techniques are used. Another issue is the drop in supply voltages. Operating critical parts at higher supply voltages by exploiting combinations of thin- and thick-oxide transistors can solve this problem. Composite transistors are presented to solve this problem in a practical way. Practical rules of thumb based on measurements are derived for the above phenomena

Limits on Fundamental Limits to Computation

An indispensable part of our lives, computing has also become essential to industries and governments. Steady improvements in computer hardware have been supported by periodic doubling of transistor densities in integrated circuits over the last fifty years. Such Moore scaling now requires increasingly heroic efforts, stimulating research in alternative hardware and stirring controversy. To help evaluate emerging technologies and enrich our understanding of integrated-circuit scaling, we review fundamental limits to computation: in manufacturing, energy, physical space, design and verification effort, and algorithms. To outline what is achievable in principle and in practice, we recall how some limits were circumvented, compare loose and tight limits. We also point out that engineering difficulties encountered by emerging technologies may indicate yet-unknown limits.Comment: 15 pages, 4 figures, 1 tabl

Beyond Power over Ethernet : the development of Digital Energy Networks for buildings

Alternating current power distribution using analogue control and safety devices has been the dominant process of power distribution within our buildings since the electricity industry began in the late 19th century. However, with advances in digital technology, the seeds of change have been growing over the last decade. Now, with the simultaneous dramatic fall in power requirements of digital devices and corresponding rise in capability of Power over Ethernet, an entire desktop environment can be powered by a single direct current (dc) Ethernet cable. Going beyond this, it will soon be possible to power entire office buildings using dc networks. This means the logic of “one-size fits all” from the existing ac system is no longer relevant and instead there is an opportunity to redesign the power topology to be appropriate for different applications, devices and end-users throughout the building. This paper proposes a 3-tier classification system for the topology of direct current microgrids in commercial buildings – called a Digital Energy Network or DEN. The first tier is power distribution at a full building level (otherwise known as the microgrid); the second tier is power distribution at a room level (the nanogrid); and the third tier is power distribution at a desktop or appliance level (the picogrid). An important aspect of this classification system is how the design focus changes for each grid. For example; a key driver of the picogrid is the usability of the network – high data rates, and low power requirements; however, in the microgrid, the main driver is high power and efficiency at low cost