Holding Dissapearance in RTD-based Quantizers

Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are on the basis of advanced circuits for communications. The operation of such quantizer has two steps : sampling and holding. Once the quantizer samples the signal, it must maintain the sampled value even if the input changes. However, holding property is not inherent to MML circuit topologies. This paper analyses the case of an MML ternary inverter used as a quantizer, and determines the relations that circuit representative parameters must verify to avoid this malfunction.Comment: Submitted on behalf of TIMA Editions (http://irevues.inist.fr/tima-editions

Atomically Thin Resonant Tunnel Diodes built from Synthetic van der Waals Heterostructures

Vertical integration of two-dimensional van der Waals materials is predicted to lead to novel electronic and optical properties not found in the constituent layers. Here, we present the direct synthesis of two unique, atomically thin, multi-junction heterostructures by combining graphene with the monolayer transition-metal dichalocogenides: MoS2, MoSe2, and WSe2.The realization of MoS2-WSe2-Graphene and WSe2-MoSe2-Graphene heterostructures leads toresonant tunneling in an atomically thin stack with spectrally narrow room temperature negative differential resistance characteristics

Monolithic integration of tunnel diode based inverters on exact (001) Si substrates

Monolithic integration of tunnel diode-based inverters on exact (001) Si substrates for the future high-speed, low-power, and compact digital circuits is demonstrated. A two-state inverter was fabricated using a forward biased fin-array tunnel diode as drive and a reverse-biased counterpart as load. On-chip operation and reduced fabrication complexity were achieved by exploiting the resistive characteristic of the reverse-biased tunnel diodes and the pre-defined patterns on the Si substrat

Quantum and spin-based tunneling devices for memory systems

Rapid developments in information technology, such as internet, portable computing, and wireless communication, create a huge demand for fast and reliable ways to store and process information. Thus far, this need has been paralleled with the revolution in solid-state memory technologies. Memory devices, such as SRAM, DRAM, and flash, have been widely used in most electronic products. The primary strategy to keep up the trend is miniaturization. CMOS devices have been scaled down beyond sub-45 nm, the size of only a few atomic layers. Scaling, however, will soon reach the physical limitation of the material and cease to yield the desired enhancement in device performance. In this thesis, an alternative method to scaling is proposed and successfully realized. The proposed scheme integrates quantum devices, Si/SiGe resonant interband tunnel diodes (RITD), with classical CMOS devices forming a microsystem of disparate devices to achieve higher performance as well as higher density. The device/circuit designs, layouts and masks involving 12 levels were fabricated utilizing a process that incorporates nearly a hundred processing steps. Utilizing unique characteristics of each component, a low-power tunneling-based static random access memory (TSRAM) has been demonstrated. The TSRAM cells exhibit bistability operation with a power supply voltage as low as 0.37 V. Various TSRAM cells were also constructed and their latching mechanisms have been extensively investigated. In addition, the operation margins of TSRAM cells are evaluated based on different device structures and temperature variation from room temperature up to 200oC. The versatility of TSRAM is extended beyond the binary system. Using multi-peak Si/SiGe RITD, various multi-valued TSRAM (MV-TSRAM) configurations that can store more than two logic levels per cell are demonstrated. By this virtue, memory density can be substantially increased. Using two novel methods via ambipolar operation and utilization of enable/disable transistors, a six-valued MV-TSRAM cell are demonstrated. A revolutionary novel concept of integrating of Si/SiGe RITD with spin tunnel devices, magnetic tunnel junctions (MTJ), has been developed. This hybrid approach adds non-volatility and multi-valued memory potential as demonstrated by theoretical predictions and simulations. The challenges of physically fabricating these devices have been identified. These include process compatibility and device design. A test bed approach of fabricating RITD-MTJ structures has been developed. In conclusion, this body of work has created a sound foundation for new research frontiers in four different major areas: integrated TSRAM system, MV-TSRAM system, MTJ/RITD-based nonvolatile MRAM, and RITD/CMOS logic circuits

Tristate memory cells using double-peaked fin-array III-V tunnel diodes monolithically grown on (001) silicon substrates

We demonstrate functional tristate memory cells using multipeaked GaAs/InGaAs fin-array tunnel diodes grown on exact (001) Si substrates. On-chip connection of single-peaked tunnel diode arrays produces I–V characteristics with multiple negative-differential resistance regions. We designed and fabricated two types of tristate memory cells. In one design, a double-peaked tunnel diode was used as the drive, and a reverse-biased single-peaked tunnel diode was used as the load. In the other design, the tristate memory cell was realized by the series connection of two forward-biased single-peaked tunnel diode

Analytic Approach to the Operation of RTD Ternary Inverters Based on MML

Open Access.Multiple-valued Logic (MVL) circuits are one of the most attractive applications of the Monostable-to-Multistable transition Logic (MML), and they are on the basis of advanced circuits for communications. However, a proper design is not inherent to the usual MML circuit topologies. This paper analyses the case of an MML ternary inverter, and determines the relations that circuit representative parameters must verify to obtain a correct behaviour.This work has been funded by the Spanish Government under project NDR, TEC2007- 67245/MIC, and the Junta de Andalucía through the Proyecto de Excelencia TIC-2961.Peer Reviewe

Fin-array tunneling trigger with tunable hysteresis on (001) silicon substrate

We report the fabrication and characterization of a GaAs fin-array tunneling trigger monolithically integrated on an exact (001) silicon substrate. A Schmitt-trigger-like behavior was observed under double sweep condition by connecting the tunnel diode with an on-chip load resistor. The tunneling trigger circuit was studied using load line analysis. Critical parameters of the circuit were extracted. We found that the circuit hysteresis can be tuned by tailoring of the diode dimensions and load resistor value

GaAs-InGaAs-GaAs fin-array tunnel diodes on (001) Si substrates with room-temperature peak-to-valley current ratio of 5.4

In this letter, we report the selective area growth of GaAs, In0.2Ga0.8As, and GaAs/In0.2Ga0.8As/GaAs quantum-well fins of 65-nm width on exactly orientated (001) Si substrates. By exploiting high aspect ratio trenches formed by patterned SiO2 on Si and a V-grooved Si (111) surface in the aspect ratio trapping process, we are able to achieve good material quality and structural properties, as evidenced by x-ray diffraction, scanning electron microscopy, and transmission electron microscopy. The fabricated GaAs-In0.2Ga0.8As-GaAs fin-array tunnel diodes exhibit a maximum room-temperature peak-to-valley current ratio of 5.4, and negative differential resistance characteristics up to 200 °C

Design of Ternary Memory Cell Using QDGFET

Ternary logic is a promising option to conventional binary logic because it can handle higher information in less number of gate count. Less number of gates requires less area in a chip which is equivalent to gold in today’s nano scale circuits. A novel design of a ternary memory cell based on QDGFETs is proposed. Memory cell is made of two back to back connected inverters. It is the conventional 6T memory cell design. Main advantage of QDGFET is that it can be used directly by replacing CMOS in the circuit without making any changes. Embedded memory requires the largest share of area in modern high-performance circuit designs. As the technology progresses the demand for high capacity memories also increases. So to fulfil this demand, researchers are trying to come up with new technology and solutions. The use of ternary logic instead of binary logic is a possible solution. So in this paper I have designed a ternary memory cell which stores one bit of ternary logic data