Non-contact Microelectronic Device Inspection Systems And Methods

Non-contact microelectronic device inspection systems and methods are discussed and provided. Some embodiments include a method of generating a virtual reference device (or chip). This approach uses a statistics to find devices in a sample set that are most similar and then averages their time domain signals to generate the virtual reference. Signals associated with the virtual reference can then be correlated with time domain signals obtained from the packages under inspection to obtain a quality signature. Defective and non-defective devices are separated by estimating a beta distribution that fits a quality signature histogram of inspected packages and determining a cutoff threshold for an acceptable quality signature. Other aspects, features, and embodiments are also claimed and described.Georgia Tech Research Corporatio

Cyclic and low temperature effects on microcircuits

Cyclic temperature and low temperature operating life tests, and pre-/post-life device evaluations were used to determine the degrading effects of thermal environments on microcircuit reliability. Low power transistor-transistor-logic gates and linear devices were included in each test group. Device metallization systems included aluminum metallization/aluminum wire, aluminum metallization/gold wire, and gold metallization/gold wire. Fewer than 2% electrical failures were observed during the cyclic and low temperature life tests and the post-life evaluations revealed approximately 2% bond pull failures. Reconstruction of aluminum die metallization was observed in all devices and the severity of the reconstruction appeared to be directly related to the magnitude of the temperature excursion. All types of bonds except the gold/gold bonds were weakened by exposure to repeated cyclic temperature stress

GSFC specification electronic data processing magnetic recording tape

The design requirements are given for magnetic oxide coated, electronic data processing tape, wound on reels. Magnetic recording tape types covered by this specification are intended for use on digital tape transports using the Non-Return-to-Zero-change-on-ones (NRZI) recording method for recording densities up to and including 800 characters per inch (cpi) and the Phase-Encoding (PE) recording method for a recording density of 1600 cpi

CdS solar cell development Interim technical report

Cadmium sulfide solar cell design criteri

Diode step stress testing program for JANTX1N3016B

The effect of power/temperature step stress when applied to a variety the zener diode JANTX2N3016B manufactured by Siemens and Motorola is reported. A total of 48 samples from each manufacturer was submitted to the process. In addition, two control sample units were maintained for verification of the electrical parametric testing

Improvements to a Thermally Actuated MEMS Viscosity Sensor

Being able to measure and monitor the viscosity of a fluid accurately and in real-time can provide insights and prevent field failures of lubricated mechanical elements. A micro electro mechanical system (MEMS) viscosity sensor that measures the properties of liquids through thermal vibrations of a silicon membrane has been previously developed. The device measures viscosity through three different characteristics: the frequency, amplitude and the quality factor of the vibrating membrane. The membrane is actuated via a short pulse of heat delivered by the heater resistor provided by an external voltage. The pulse width is controlled by a waveform generator and a power MOSFET. The movement of the membrane is measured with an in-situ piezoresistor Wheatstone bridge, which is powered by an external voltage source, and amplified with and instrumentational amplifier before the resulting vibrating signal is analyzed in LabView. The end goal of this work is to characterize the sensitivity and real-time response of a thermally actuated MEMS viscosity sensor. In addition, a process modification to include a deep reactive ion etch instead of a KOH etch, has been developed. As viscosity is dependent on temperature, when the membrane is actuated by heat, the effects of locally changing the fluid temperature will affect the sensitivity of the sensor. Optimized test bias condition results were, Wheatstone bridge bias voltage when increased over 7 V, the natural frequency of vibration of the sensor is modified. Pulse width and heater bias value can be adjusted for optimum sensor response. With these established bias conditions, the real-time response of the system was investigated. Epoxy was used to cover the sensor perimeter, protect the 25 - micron aluminum wire bond connections to a copper PCB and to glue the sensor onto the PCB. Test result show a spike in frequency and amplitude when different oils were added. As shown with additional tests, the spike is mainly caused by slight temperature variations that are introduced with new oil and how they affect the sensor packaging. Spikes were reduced by lowering the bridge bias voltage from 7 V to 3 V, which minimized the sensor heating. Furthermore, addition of oil in very small quantities, in the µL range, reduced the changes in temperature. Figure 1 shows frequency and amplitude response with varying viscosities without agitation. During testing, when oil is added, the amplitude shows an immediate overdamped response which takes about 1-2 minutes to stabilize, whereas frequency is characterized by an underdamped response with response time 5-7 minutes. Frequency response time was slower as it is very dependent on intrinsic stresses of both sensor and packaging, whereas amplitude of oscillations seems to be more independent to these properties changing and shows faster response

Characterization of Thermo-Mechanical Damage in Tin and Sintered Nano-Silver Solders

abstract: Increasing density of microelectronic packages, results in an increase in thermal and mechanical stresses within the various layers of the package. To accommodate the high-performance demands, the materials used in the electronic package would also require improvement. Specifically, the damage that often occurs in solders that function as die-attachment and thermal interfaces need to be addressed. This work evaluates and characterizes thermo-mechanical damage in two material systems – Electroplated Tin and Sintered Nano-Silver solder. Tin plated electrical contacts are prone to formation of single crystalline tin whiskers which can cause short circuiting. A mechanistic model of their formation, evolution and microstructural influence is still not fully understood. In this work, growth of mechanically induced tin whiskers/hillocks is studied using in situ Nano-indentation and Electron Backscatter Diffraction (EBSD). Electroplated tin was indented and monitored in vacuum to study growth of hillocks without the influence of atmosphere. Thermal aging was done to study the effect of intermetallic compounds. Grain orientation of the hillocks and the plastically deformed region surrounding the indent was studied using Focused Ion Beam (FIB) lift-out technique. In addition, micropillars were milled on the surface of electroplated Sn using FIB to evaluate the yield strength and its relation to Sn grain size. High operating temperature power electronics use wide band-gap semiconductor devices (Silicon Carbide/Gallium Nitride). The operating temperature of these devices can exceed 250oC, preventing use of traditional Sn-solders as Thermal Interface materials (TIM). At high temperature, the thermomechanical stresses can severely degrade the reliability and life of the device. In this light, new non-destructive approach is needed to understand the damage mechanism when subjected to reliability tests such as thermal cycling. In this work, sintered nano-Silver was identified as a promising high temperature TIM. Sintered nano-Silver samples were fabricated and their shear strength was evaluated. Thermal cycling tests were conducted and damage evolution was characterized using a lab scale 3D X-ray system to periodically assess changes in the microstructure such as cracks, voids, and porosity in the TIM layer. The evolution of microstructure and the effect of cycling temperature during thermal cycling are discussed.Dissertation/ThesisDoctoral Dissertation Materials Science and Engineering 201

High Temperature LTCC based SiC Double-sided Cooling Power Electronic Module

This objective of this dissertation research is to investigate a module packaging technology for high temperature double-sided cooling power electronic module application. A high-temperature wire-bondless low-temperature co-fired ceramic (LTCC) based double-sided cooling power electronic module was designed, simulated and fabricated. In this module, the conventional copper base plate is removed to reduce the thermal resistance between the device junctions to the heat sink and to improve the reliability of the module by eliminating the large area solder joint between the power substrate and the copper base plate. A low-temperature co-fired ceramic (LTCC) substrate with cavities and vias is used as the dielectric material between the top and bottom substrates and it also serves as the die frame. A nano silver attach material is used to enable the high-temperature operation. Thermal and thermo-mechanical simulations were performed to evaluate the advantages of the LTCC double-sided power module structure and compared to other reported module structures and its wire-bonded counterpart. The junction-to-case thermal resistance for the power module without a copper base plate is 0.029oC/W, which is smaller than that of the power module with a copper base plate. Thermo-mechanical simulation reveals that double-sided cooling power modules generate higher thermal stresses when compared to that of the single-sided cooling power modules which indicates the trade-off between the junction temperature and the thermo-mechanical stress. Electrical and thermal characterizations were performed to test the functionality of the fabricated module using a 1200V rated voltage blocking capability. The forward and reverse characteristics of the SiC power MOSFET and SiC diode module were tested to 200°C and they demonstrated the functionality of the power module. The junction-to-ambient thermal resistance of the proposed module is shown to reduce by 11% compared to the wire-bonded equivalent which shows an improvement of the thermal performance of the double-sided cooling structure. Finally, the reliability of the several power substrates was evaluated based on the thermal stress and fatigue life simulation of the bonding layer to determine the mechanical weakest spots of the power module. Thermal cycling experiments were also conducted to validate the simulation results

Methods and Results of Power Cycling Tests for Semiconductor Power Devices

This work intends to enhance the state of the research in power cycling tests with statements on achievable measurement accuracy, proposed test bench topologies and recommendations on improved test strategies for various types of semiconductor power devices. Chapters 1 and 2 describe the current state of the power cycling tests in the context of design for reliability comprising applicable standards and lifetime models. Measurement methods in power cycling tests for the essential physical parameters are explained in chapter 3. The dynamic and static measurement accuracy of voltage, current and temperature are discussed. The feasibly achievable measurement delay tmd of the maximal junction temperature Tjmax, its consequences on accuracy and methods to extrapolate to the time point of the turn-off event are explained. A method to characterize the thermal path of devices to the heatsink via measurements of the thermal impedance Zth is explained. Test bench topologies starting from standard setups, single to multi leg DC benches are discussed in chapter 4. Three application-closer setups implemented by the author are explained. For tests on thyristors a test concept with truncated sinusoidal current waveforms and online temperature measurement is introduced. An inverter-like topology with actively switching IGBTs is presented. In contrast to standard setups, there the devices under test prove switching capability until reaching the end-of-life criteria. Finally, a high frequency switching topology with low DC-link voltage and switching losses contributing significantly to the overall power losses is presented providing new degrees of freedom for setting test conditions. The particularities of semiconductor power devices in power cycling tests are thematized in chapter 5. The first part describes standard packages and addressed failure mechanisms in power cycling. For all relevant power electronic devices in silicon and silicon carbide, the devices’ characteristics, methods for power cycling and their consequences for test results are explained. The work is concluded and suggestions for future work are given in chapter 6.:Abstract 1 Kurzfassung 3 Acknowledgements 5 Nomenclature 10 Abbreviations 10 Symbols 12 1 Introduction 19 2 Applicable Standards and Lifetime Models 25 3 Measurement parameters in power cycling tests 53 4 Test Bench Topologies 121 5 Semiconductor Power Devices in Power Cycling 158 6 Conclusion and Outlook 229 References 235 List of Publications 253 Theses 257Diese Arbeit bereichert den Stand der Wissenschaft auf dem Gebiet von Lastwechseltests mit Beiträgen zu verbesserter Messgenauigkeit, vorgeschlagenen Teststandstopologien und verbesserten Teststrategien für verschiedene Arten von leistungselektronischen Bauelementen. Kurzgefasst der Methodik von Lastwechseltests. Das erste Themengebiet in Kapitel 1 und Kapitel 2 beschreibt den aktuellen Stand zu Lastwechseltests im Kontext von Design für Zuverlässigkeit, welcher in anzuwendenden Standards und publizierten Lebensdauermodellen dokumentiert ist. Messmethoden für relevante physikalische Parameter in Lastwechseltests sind in Kapitel 3. erläutert. Zunächst werden dynamische und statische Messgenauigkeit für Spannung, Strom und Temperaturen diskutiert. Die tatsächlich erreichbare Messverzögerung tMD der maximalen Sperrschichttemperatur Tjmax und deren Auswirkung auf die Messgenauigkeit der Lastwechselfestigkeit wird dargelegt. Danach werden Methoden zur Rückextrapolation zum Zeitpunkt des Abschaltvorgangs des Laststroms diskutiert. Schließlich wird die Charakterisierung des Wärmepfads vom Bauelement zur Wärmesenke mittels Messung der thermischen Impedanz Zth behandelt. In Kapitel 4 werden Teststandstopologien beginnend mit standardmäßig genutzten ein- und mehrsträngigen DC-Testständen vorgestellt. Drei vom Autor umgesetzte anwendungsnahe Topologien werden erklärt. Für Tests mit Thyristoren wird ein Testkonzept mit angeschnittenem sinusförmigem Strom und in situ Messung der Sperrschichttemperatur eingeführt. Eine umrichterähnliche Topologie mit aktiv schaltenden IGBTs wird vorgestellt. Zuletzt wird eine Topologie mit hoch frequent schaltenden Prüflingen an niedriger Gleichspannung bei der Schaltverluste signifikant zur Erwärmung der Prüflinge beitragen vorgestellt. Dies ermöglicht neue Freiheitsgrade um Testbedingungen zu wählen. Die Besonderheiten von leistungselektronischen Bauelementen werden in Kapitel 5 thematisiert. Der erste Teil beschreibt Gehäusetypen und adressierte Fehlermechanismen in Lastwechseltests. Für alle untersuchten Bauelementtypen in Silizium und Siliziumkarbid werden Charakteristiken, empfohlene Methoden für Lastwechseltests und Einflüsse auf Testergebnisse erklärt. Die Arbeit wird in Kapitel 6 zusammengefasst und Vorschläge zu künftigen Arbeiten werden unterbreitet.:Abstract 1 Kurzfassung 3 Acknowledgements 5 Nomenclature 10 Abbreviations 10 Symbols 12 1 Introduction 19 2 Applicable Standards and Lifetime Models 25 3 Measurement parameters in power cycling tests 53 4 Test Bench Topologies 121 5 Semiconductor Power Devices in Power Cycling 158 6 Conclusion and Outlook 229 References 235 List of Publications 253 Theses 25

Infrared telescope

The development of the Infrared Telescope for Spacelab 2 is discussed. The design, development, and testing required to interface a stationary superfluid helium dewar with a scanning cryostate capable of operating in the zero-g environment in the space shuttle bay is described