NMOS DEVICE OPTIMIZATION AND FABRICATION USING ATHENA & ATLAS SIMULATION SOFTWARE

Experiment has proven that NMOS performs better than PMOS due to higher drive current, higher mobility, easier to implement scaling technology and low power consumption. However, there is still room for further optimization as the technology trend for the miniaturization ofNMOS and integrated devices continue to grow. In this project, several objectives have been outlined to be completed within 2 semester period. These include detailed understanding of fabrication aspect and NMOS properties, optimizing NMOS by reducing threshold voltage, minimizing off-stage leakage, reducing gate length, increasing switching speed and designing a mixed mode circuit. However, the cost required to perform experimental analysis and optimization of semiconductor devices using fabrication process can be very expensive especially when involving purchase of expensive electrical testing equipment. Thus, it is recommended to perform optimization and analysis using simulation. One ofthe best device process and simulation tool is Silvaco ATHENA & ATLAS simulation software. It provides user with various capability in process and electrical testing. After manipulating and improving process parameters, the optimized device has recorded significant improvement over the predecessor. Optimizations include better threshold voltage extraction (0.2v), drain current rise beyond pinch off, better drain current extraction, higher switching speed at 2Ghz, better device structure after ion implantation due to tilted implantation, lower off-stage leakage current (1.2589 x 10' A/um) and minimization ofjunction breakdown effect

A novel deep submicron bulk planar sizing strategy for low energy subthreshold standard cell libraries

Engineering andPhysical Science ResearchCouncil (EPSRC) and Arm Ltd for providing funding in the form of grants and studentshipsThis work investigates bulk planar deep submicron semiconductor physics in an attempt to improve standard cell libraries aimed at operation in the subthreshold regime and in Ultra Wide Dynamic Voltage Scaling schemes. The current state of research in the field is examined, with particular emphasis on how subthreshold physical effects degrade robustness, variability and performance. How prevalent these physical effects are in a commercial 65nm library is then investigated by extensive modeling of a BSIM4.5 compact model. Three distinct sizing strategies emerge, cells of each strategy are laid out and post-layout parasitically extracted models simulated to determine the advantages/disadvantages of each. Full custom ring oscillators are designed and manufactured. Measured results reveal a close correlation with the simulated results, with frequency improvements of up to 2.75X/2.43X obs erved for RVT/LVT devices respectively. The experiment provides the first silicon evidence of the improvement capability of the Inverse Narrow Width Effect over a wide supply voltage range, as well as a mechanism of additional temperature stability in the subthreshold regime. A novel sizing strategy is proposed and pursued to determine whether it is able to produce a superior complex circuit design using a commercial digital synthesis flow. Two 128 bit AES cores are synthesized from the novel sizing strategy and compared against a third AES core synthesized from a state-of-the-art subthreshold standard cell library used by ARM. Results show improvements in energy-per-cycle of up to 27.3% and frequency improvements of up to 10.25X. The novel subthreshold sizing strategy proves superior over a temperature range of 0 °C to 85 °C with a nominal (20 °C) improvement in energy-per-cycle of 24% and frequency improvement of 8.65X. A comparison to prior art is then performed. Valid cases are presented where the proposed sizing strategy would be a candidate to produce superior subthreshold circuits

Selective Dry Etch for Defining Ohmic Contacts for High Performance ZnO TFTs

Recently, gigahertz RF performance has been demonstrated in zinc oxide (ZnO) TFT. However, the need arises for sub-micron channel length (Lc) dimensions to extend these results into X-band frequency range of operation. This thesis is a pioneering effort identifying device access materials to be selectively etched to ZnO via plasma-assisted etch (PAE) to avoid processing limitations from traditional optical lithography channel definition methods. A subtractive etch process using CF4/O2 gas mixture was completed with various Ohmic contact materials to ZnO providing foundational research upon which nano-scale, high-frequency ZnO thin-film transistors (TFTs) could be fabricated. Molybdenum, tantalum, titanium tungsten 10-90, and tungsten metallic contact schemes to ZnO are investigated for their etch selectivities to ZnO and etch profiles. Tungsten displayed promising device scalability results with excellent aspect ratio and 200nm Lc. A new semiconductor-semiconductor contact interface to ZnO using nc-Si is initially reported with 15mA/mm current density and 18mS/mm transconductance. Nc-Si also displays promising scaling results through the subtractive etch process defined with e-beam lithography. Results included 157nm channel length, high aspect ratio, and high extrapolated current density of nearly 1A/mm at 100nm Lc and gate and drain voltages of 10V

NMOS DEVICE OPTIMIZATION AND FABRICATION USING ATHENA & ATLAS SIMULATION SOFTWARE

Experiment has proven that NMOS performs better than PMOS due to higher drive current, higher mobility, easier to implement scaling technology and low power consumption. However, there is still room for further optimization as the technology trend for the miniaturization ofNMOS and integrated devices continue to grow. In this project, several objectives have been outlined to be completed within 2 semester period. These include detailed understanding of fabrication aspect and NMOS properties, optimizing NMOS by reducing threshold voltage, minimizing off-stage leakage, reducing gate length, increasing switching speed and designing a mixed mode circuit. However, the cost required to perform experimental analysis and optimization of semiconductor devices using fabrication process can be very expensive especially when involving purchase of expensive electrical testing equipment. Thus, it is recommended to perform optimization and analysis using simulation. One ofthe best device process and simulation tool is Silvaco ATHENA & ATLAS simulation software. It provides user with various capability in process and electrical testing. After manipulating and improving process parameters, the optimized device has recorded significant improvement over the predecessor. Optimizations include better threshold voltage extraction (0.2v), drain current rise beyond pinch off, better drain current extraction, higher switching speed at 2Ghz, better device structure after ion implantation due to tilted implantation, lower off-stage leakage current (1.2589 x 10' A/um) and minimization ofjunction breakdown effect

Dual material gate field effect transistor (DMG-FET)

Improving performance and suppressing short channel effects are two of the most important issues in present field effect transistors development. Hence, high performance and long channel like behaviors are essential requirements for short channel FETs. This dissertation focuses on new ways to achieve these significant goals. A new field effect transistor - dual material gate FET (DMG-FET) - is presented for the first time. The unique feature of the DMG-FET is its gate which consists of two laterally contacting gate materials with different work functions. This novel gate structure takes advantage of material work function difference in such a way that charge carriers are accelerated more rapidly in the channel and the channel potential near the source is screened from the drain bias after saturation. Using HFET as a vehicle, it is shown that the drive current and transconductance in DMG-FET are therefore substantially enhanced as compared to conventional FET. Moreover, it is observed that the short channel effects such as channel length modulation, DIBL and hot-carrier effect are significantly suppressed. Numerical simulations are employed to investigate the new device structure and related phenomenon. A simple and practical DMG-HFET fabrication process has been developed. The proposed DMG-HFET is thus realized for the first time. Experimental results exhibit improved characteristics as the simulation results predicted

Design and modelling of variability tolerant on-chip communication structures for future high performance system on chip designs

The incessant technology scaling has enabled the integration of functionally complex System-on-Chip (SoC) designs with a large number of heterogeneous systems on a single chip. The processing elements on these chips are integrated through on-chip communication structures which provide the infrastructure necessary for the exchange of data and control signals, while meeting the strenuous physical and design constraints. The use of vast amounts of on chip communications will be central to future designs where variability is an inherent characteristic. For this reason, in this thesis we investigate the performance and variability tolerance of typical on-chip communication structures. Understanding of the relationship between variability and communication is paramount for the designers; i.e. to devise new methods and techniques for designing performance and power efficient communication circuits in the forefront of challenges presented by deep sub-micron (DSM) technologies. The initial part of this work investigates the impact of device variability due to Random Dopant Fluctuations (RDF) on the timing characteristics of basic communication elements. The characterization data so obtained can be used to estimate the performance and failure probability of simple links through the methodology proposed in this work. For the Statistical Static Timing Analysis (SSTA) of larger circuits, a method for accurate estimation of the probability density functions of different circuit parameters is proposed. Moreover, its significance on pipelined circuits is highlighted. Power and area are one of the most important design metrics for any integrated circuit (IC) design. This thesis emphasises the consideration of communication reliability while optimizing for power and area. A methodology has been proposed for the simultaneous optimization of performance, area, power and delay variability for a repeater inserted interconnect. Similarly for multi-bit parallel links, bandwidth driven optimizations have also been performed. Power and area efficient semi-serial links, less vulnerable to delay variations than the corresponding fully parallel links are introduced. Furthermore, due to technology scaling, the coupling noise between the link lines has become an important issue. With ever decreasing supply voltages, and the corresponding reduction in noise margins, severe challenges are introduced for performing timing verification in the presence of variability. For this reason an accurate model for crosstalk noise in an interconnection as a function of time and skew is introduced in this work. This model can be used for the identification of skew condition that gives maximum delay noise, and also for efficient design verification

Science Mission Directorate TechPort Records for 2019 STI-DAA Release

The role of the Science Mission Directorate (SMD) is to enable NASA to achieve its science goals in the context of the Nation's science agenda. SMD's strategic decisions regarding future missions and scientific pursuits are guided by Agency goals, input from the science community including the recommendations set forth in the National Research Council (NRC) decadal surveys and a commitment to preserve a balanced program across the major science disciplines. Toward this end, each of the four SMD science divisions -- Heliophysics, Earth Science, Planetary Science, and Astrophysics -- develops fundamental science questions upon which to base future research and mission programs

Ultra-thin plasma nitrided oxide gate dielectrics for advanced MOS transistors

Ultra-thin plasma nitrided oxides have been optimized with the objective to decrease JG and maximize carrier mobility. It was found that while the base oxide cannot be aggressively scaled, plasma optimization yields better mobility thereby increase transistor performance. A summary of the EOT versus gate leakage current density of NMOS devices with plasma nitrided oxides is shown in Figure 5.19. EOT down to 1.2 nm has been achieved with a gate leakage current density of 40 A/cm2 at 1 V operating voltage

Biomimetic nanostructured surfaces for antireflection in photovoltaics

A key consideration in the design of any solar cell is the reduction of reflectance from the top surface. Traditional thin film antireflection schemes are being challenged by new techniques that involve texturing on the subwavelength scale to form ‘moth-eye’ arrays, so called because they are inspired by Nature’s answer to unwanted reflections, the arrays of pillars found on the eyes and wings of some species of moth. In this work, a new method is presented for the optimization of thin film coatings that accounts for the angular and spectral variations in incident solar radiation from sunrise to sunset. This approach is then extended to silicon moth-eye arrays to assess how effectively these surfaces can provide antireflection for silicon solar cells over a full day. The reflectance spectra of moth-eye surfaces are found to depend on the period of the arrays and the height and shape of the pillars, and consequently these parameters can be optimized for the solar spectrum. Simulations predict that replacing an optimized double layer thin film coating with a moth-eye array could increase the full day cell performance by 2% for a laboratory cell and 3% for an encapsulated cell. Compared to a perfectly transmitting interface, this corresponds to losses in short circuit current of only 5.3% and 0.6% for a laboratory and an encapsulated cell, respectively. Furthermore, fabrication of silicon moth-eye arrays by electron beam lithography and dry etching leads to predicted percentage losses at peak irradiance, compared to an ideal antireflective surface, of only 1%. The potentially more scalable technique of nanoimprint lithography is also used to fabricate antireflective moth-eye arrays in silicon, over areas as large as 1 cm2, demonstrating great potential for stealth and antiglare applications in addition to photovoltaics