Network Management and Control for mmWave Communications

Millimeter-wave (mmWave) is one of the key technologies that enables the next wireless generation. mmWave offers a much higher bandwidth than sub-6GHz communications which allows multi-gigabit-per-second rates. This also alleviates the scarcity of spectrum at lower frequencies, where most devices connect through sub-6GHz bands. However new techniques are necessary to overcome the challenges associated with such high frequencies. Most of these challenges come from the high spatial attenuation at the mmWave band, which requires new paradigms that differ from sub-6GHz communications. Most notably mmWave telecommunications are characterized by the need to be directional in order to extend the operational range. This is achieved by using electronically steerable antenna arrays, that focus the energy towards the desired direction by combining each antenna element constructively or destructively. Additionally, most of the energy comes from the Line Of Sight (LOS) component which gives mmWave a quasi-optical behaviour where signals can reflect off walls and still be used for communication. Some other challenges that directional communications bring are mobility tracking, blockages and misalignments due to device rotation. The IEEE 802.11ad amendment introduced wireless telecommunications in the unlicensed 60 GHz band. It is the first standard to address the limitations of mmWave. It does so by introducing new mechanisms at the Medium Access Control (MAC) and Physical (PHY) layers. It introduces multi-band operation, relay operation mode, hybrid channel access scheme, beam tracking and beam forming among others. In this thesis we present a series of works that aim to improve mmWave telecommunications. First we give an overview of the intrinsic challenges of mmWave telecommunications, by explaining the modifications to the MAC and PHY layers. This sets the base for the rest of the thesis. Then do a comprehensive study on how mmWave behaves with existing technologies, namely TCP. TCP is unable to distinguish losses caused by congestion or by transmission errors caused by channel degradation. Since mmWave is affected by blockages more than sub-6GHz technologies, we propose a set of parameters that improve the channel quality even for mobile scenarios. The next job focuses on reducing the initial access overhead of mmWave by using sub-6GHz information to steer towards the desired direction. We start this work by doing a comprehensive High Frequency (HF) and Low Frequency (LF) correlation, analyzing the similarity of the existing paths between the two selected frequencies. Then we propose a beam steering algorithm that reduces the overhead to one third of the original time. Once we have studied how to reduce the initial access overhead, we propose a mechanism to reduce the beam tracking overhead. For this we propose an open platform based on a Field Programmable Gate Arrays (FPGA) where we implement an algorithm that completely removes the need to train on the Station (STA) side. This is achieved by changing beam patterns on the STA side while the Access Point (AP) is sending the preamble. We can change up to 10 beam patterns without losing connection and we reduce the overhead by a factor of 8.8 with respect to the IEEE 802.11ad standard. Finally we present a dual band location system based on Commercial-Off-The-Shelve (COTS) devices. Locating the STA can improve the quality of the channel significantly, since the AP can predict and react to possible blockages. First we reverse engineer existing 60 GHz enabled COTS devices to extract Channel State Information (CSI) and Fine Timing Measurements (FTM) measurements, from which we can estimate angle and distance. Then we develop an algorithm that is able to choose between HF and LF in order to improve the overall accuracy of the system. We achieve less than 17 cm of median error in indoor environments, even when some areas are Non Line Of Sight (NLOS).This work has been supported by IMDEA Networks Institute.Programa de Doctorado en Ingeniería Telemática por la Universidad Carlos III de MadridPresidente: Matthias Hollick.- Secretario: Vincenzo Mancuso.- Vocal: Paolo Casar

Developing a support for FPGAs in the Controller parallel programming model

La computación heterogénea se presenta como la solución para conseguir supercomputadores cada vez más rápidos capaces de resolver problemas más grandes y complejos en diferentes áreas de conocimiento. Para ello, integra aceleradores con distintas arquitecturas capaces de explotar las características de los problemas desde distintos enfoques obteniendo, de este modo, un mayor rendimiento. Las FPGAs son hardware reconfigurable, i.e., es posible modificarlas después de su fabricación. Esto permite una gran flexibilidad y una máxima adaptación al problema en cuestión. Además, tienen un consumo energético muy bajo. Todas estas ventajas tienen el gran inconveniente de una más difícil programaci ón mediante los propensos a errores HDLs (Hardware Description Language), tales como Verilog o VHDL, y requisitos de conocimientos avanzados de electrónica digital. En los últimos años los principales fabricantes de FPGAs han enfocado sus esfuerzos en desarrollar herramientas HLS (High Level Synthesis) que permiten programarlas a través de lenguajes de programación de alto nivel estilo C. Esto ha favorecido su adopción por la comunidad HPC y su integración en los nuevos supercomputadores. Sin embargo, el programador aún tiene que ocuparse de aspectos como la gestión de colas de comandos, parámetros de lanzamiento o transferencias de datos. El modelo Controller es una librería que facilita la gestión de la coordinación, comunicación y los detalles de lanzamiento de los kernels en aceleradores hardware. Explota de forma transparente sus modelos de programación nativos, en concreto OpenCL y CUDA, y, por tanto, consigue un alto rendimiento independientemente del compilador. Permite al programador utilizar los distintos recursos hardware disponibles de forma combinada en entornos heterogéneos. Este trabajo extiende el modelo Controller mediante el desarrollo de un backend que permite la integración de FPGAs, manteniendo los cambios sobre la interfaz de usuario al mínimo. A través de los resultados experimentales se comprueba que se consigue una disminución del esfuerzo de programación significativa en comparación con la implementación nativa en OpenCL. Del mismo modo, se consigue un elevado solapamiento entre computación y comunicación y un sobrecoste por el uso de la librería despreciable.Heterogeneous computing appears to be the solution to achieve ever faster computers capable of solving bigger and more complex problems in difierent fields of knowledge. To that end, it integrates accelerators with difierent architectures capable of exploiting the features of problems from difierent perspectives thus achieving higher performance. FPGAs are reconfigurable hardware, i.e., it is possible to modify them after manufacture. This allows great flexibility and maximum adaptability to the given problem. In addition, they have low power consumption. All these advantages have the great objection of more dificult programming with the errorprone HDLs (Hardware Description Language), such as Verilog or VHDL, and the requirement of advanced knowledge of digital electronics. The main FPGA vendors have concentrated on developing HLS (High Level Synthesis) tools that allow to program them with C-like high level programming languages. This favoured their adoption by the HPC community and their integration in new supercomputers. However, the programmer still has to take care of aspects such as management of command queues, launching parameters or data transfers. The Controller model is a library to easily manage the coordination, communication and kernel launching details on hardware accelerators. It transparently exploits their native or vendor specific programming models, namely OpenCL and CUDA, thus enabling the potential performance obtained by using them in a compiler agnostic way. It is intended to enable the programmer to make use of the diferent available hardware resources in combination in heterogeneous environments. This work extends the Controller model through the development of a backend that allows the integration of FPGAs, keeping the changes over the user-facing interface to the minimum. The experimental results validate that a significant decrease in programming effort compared to the native OpenCL implementation is achieved. Similarly, high overlap of computation and communication and a negligible overhead due to the use of the library are attained.Grado en Ingeniería Informátic

Fpga-based Design Of A Maximum-power-point Tracking System For Space A

Satellites need a source of power throughout their missions to help them remain operational for several years. The power supplies of these satellites, provided primarily by solar arrays, must have high efficiencies and low weights in order to meet stringent design constraints. Power conversion from these arrays is required to provide robust and reliable conversion which performs optimally in varying conditions of peak power, solar flux, and occlusion conditions. Since the role of these arrays is to deliver power, one of the principle factors in achieving maximum power output from an array is tracking and holding its maximum-power point. This point, which varies with temperature, insolation, and loading conditions, must be continuously monitored in order to react to rapid changes. Until recently, the control of maximum power point tracking (MPPT) has been implemented in microcontrollers and digital signal processors (DSPs). While DSPs can provide a reasonable performance, they do not provide the advantages that field-programmable gate arrays (FPGA) chips can potentially offer to the implementation of MPPT control. In comparison to DSP implementations, FPGAs offer lower cost implementations since the functions of various components can be integrated onto the same FPGA chip as opposed to DSPs which can perform only DSP-related computations. In addition, FPGAs can provide equivalent or higher performance with the customization potential of an ASIC. Because FPGAs can be reprogrammed at any time, repairs can be performed in-situ while the system is running thus providing a high degree of robustness. Beside robustness, this reprogrammability can provide a high level of (i) flexibility that can make upgrading an MPPT control system easy by merely updating or modifying the MPPT algorithm running on the FPGA chip, and (ii) expandability that makes expanding an FPGA-based MPPT control system to handle multi-channel control. In addition, this reprogrammability provides a level of testability that DSPs cannot match by allowing the emulation of the entire MPPT control system onto the FPGA chip. This thesis proposes an FPGA-based implementation of an MPPT control system suitable for space applications. At the core of this system, the Perturb-and-observe algorithm is used to track the maximum power point. The algorithm runs on an Alera FLEX 10K FPGA chip. Additional functional blocks, such as the ADC interface, FIR filter, dither generator, and DAC interface, needed to support the MPPT control system are integrated within the same FPGA device thus streamlining the part composition of the physical prototype used to build this control system

Real-Time Waveform Prototyping

Mobile Netzwerke der fünften Generation zeichen sich aus durch vielfältigen Anforderungen und Einsatzszenarien. Drei unterschiedliche Anwendungsfälle sind hierbei besonders relevant: 1) Industrie-Applikationen fordern Echtzeitfunkübertragungen mit besonders niedrigen Ausfallraten. 2) Internet-of-things-Anwendungen erfordern die Anbindung einer Vielzahl von verteilten Sensoren. 3) Die Datenraten für Anwendung wie z.B. der Übermittlung von Videoinhalten sind massiv gestiegen. Diese zum Teil gegensätzlichen Erwartungen veranlassen Forscher und Ingenieure dazu, neue Konzepte und Technologien für zukünftige drahtlose Kommunikationssysteme in Betracht zu ziehen. Ziel ist es, aus einer Vielzahl neuer Ideen vielversprechende Kandidatentechnologien zu identifizieren und zu entscheiden, welche für die Umsetzung in zukünftige Produkte geeignet sind. Die Herausforderungen, diese Anforderungen zu erreichen, liegen jedoch jenseits der Möglichkeiten, die eine einzelne Verarbeitungsschicht in einem drahtlosen Netzwerk bieten kann. Daher müssen mehrere Forschungsbereiche Forschungsideen gemeinsam nutzen. Diese Arbeit beschreibt daher eine Plattform als Basis für zukünftige experimentelle Erforschung von drahtlosen Netzwerken unter reellen Bedingungen. Es werden folgende drei Aspekte näher vorgestellt: Zunächst erfolgt ein Überblick über moderne Prototypen und Testbed-Lösungen, die auf großes Interesse, Nachfrage, aber auch Förderungsmöglichkeiten stoßen. Allerdings ist der Entwicklungsaufwand nicht unerheblich und richtet sich stark nach den gewählten Eigenschaften der Plattform. Der Auswahlprozess ist jedoch aufgrund der Menge der verfügbaren Optionen und ihrer jeweiligen (versteckten) Implikationen komplex. Daher wird ein Leitfaden anhand verschiedener Beispiele vorgestellt, mit dem Ziel Erwartungen im Vergleich zu den für den Prototyp erforderlichen Aufwänden zu bewerten. Zweitens wird ein flexibler, aber echtzeitfähiger Signalprozessor eingeführt, der auf einer software-programmierbaren Funkplattform läuft. Der Prozessor ermöglicht die Rekonfiguration wichtiger Parameter der physikalischen Schicht während der Laufzeit, um eine Vielzahl moderner Wellenformen zu erzeugen. Es werden vier Parametereinstellungen 'LLC', 'WiFi', 'eMBB' und 'IoT' vorgestellt, um die Anforderungen der verschiedenen drahtlosen Anwendungen widerzuspiegeln. Diese werden dann zur Evaluierung der die in dieser Arbeit vorgestellte Implementierung herangezogen. Drittens wird durch die Einführung einer generischen Testinfrastruktur die Einbeziehung externer Partner aus der Ferne ermöglicht. Das Testfeld kann hier für verschiedenste Experimente flexibel auf die Anforderungen drahtloser Technologien zugeschnitten werden. Mit Hilfe der Testinfrastruktur wird die Leistung des vorgestellten Transceivers hinsichtlich Latenz, erreichbarem Durchsatz und Paketfehlerraten bewertet. Die öffentliche Demonstration eines taktilen Internet-Prototypen, unter Verwendung von Roboterarmen in einer Mehrbenutzerumgebung, konnte erfolgreich durchgeführt und bei mehreren Gelegenheiten präsentiert werden.:List of figures List of tables Abbreviations Notations 1 Introduction 1.1 Wireless applications 1.2 Motivation 1.3 Software-Defined Radio 1.4 State of the art 1.5 Testbed 1.6 Summary 2 Background 2.1 System Model 2.2 PHY Layer Structure 2.3 Generalized Frequency Division Multiplexing 2.4 Wireless Standards 2.4.1 IEEE 802.15.4 2.4.2 802.11 WLAN 2.4.3 LTE 2.4.4 Low Latency Industrial Wireless Communications 2.4.5 Summary 3 Wireless Prototyping 3.1 Testbed Examples 3.1.1 PHY - focused Testbeds 3.1.2 MAC - focused Testbeds 3.1.3 Network - focused testbeds 3.1.4 Generic testbeds 3.2 Considerations 3.3 Use cases and Scenarios 3.4 Requirements 3.5 Methodology 3.6 Hardware Platform 3.6.1 Host 3.6.2 FPGA 3.6.3 Hybrid 3.6.4 ASIC 3.7 Software Platform 3.7.1 Testbed Management Frameworks 3.7.2 Development Frameworks 3.7.3 Software Implementations 3.8 Deployment 3.9 Discussion 3.10 Conclusion 4 Flexible Transceiver 4.1 Signal Processing Modules 4.1.1 MAC interface 4.1.2 Encoding and Mapping 4.1.3 Modem 4.1.4 Post modem processing 4.1.5 Synchronization 4.1.6 Channel Estimation and Equalization 4.1.7 Demapping 4.1.8 Flexible Configuration 4.2 Analysis 4.2.1 Numerical Precision 4.2.2 Spectral analysis 4.2.3 Latency 4.2.4 Resource Consumption 4.3 Discussion 4.3.1 Extension to MIMO 4.4 Summary 5 Testbed 5.1 Infrastructure 5.2 Automation 5.3 Software Defined Radio Platform 5.4 Radio Frequency Front-end 5.4.1 Sub 6 GHz front-end 5.4.2 26 GHz mmWave front-end 5.5 Performance evaluation 5.6 Summary 6 Experiments 6.1 Single Link 6.1.1 Infrastructure 6.1.2 Single Link Experiments 6.1.3 End-to-End 6.2 Multi-User 6.3 26 GHz mmWave experimentation 6.4 Summary 7 Key lessons 7.1 Limitations Experienced During Development 7.2 Prototyping Future 7.3 Open points 7.4 Workflow 7.5 Summary 8 Conclusions 8.1 Future Work 8.1.1 Prototyping Workflow 8.1.2 Flexible Transceiver Core 8.1.3 Experimental Data-sets 8.1.4 Evolved Access Point Prototype For Industrial Networks 8.1.5 Testbed Standardization A Additional Resources A.1 Fourier Transform Blocks A.2 Resource Consumption A.3 Channel Sounding using Chirp sequences A.3.1 SNR Estimation A.3.2 Channel Estimation A.4 Hardware part listThe demand to achieve higher data rates for the Enhanced Mobile Broadband scenario and novel fifth generation use cases like Ultra-Reliable Low-Latency and Massive Machine-type Communications drive researchers and engineers to consider new concepts and technologies for future wireless communication systems. The goal is to identify promising candidate technologies among a vast number of new ideas and to decide, which are suitable for implementation in future products. However, the challenges to achieve those demands are beyond the capabilities a single processing layer in a wireless network can offer. Therefore, several research domains have to collaboratively exploit research ideas. This thesis presents a platform to provide a base for future applied research on wireless networks. Firstly, by giving an overview of state-of-the-art prototypes and testbed solutions. Secondly by introducing a flexible, yet real-time physical layer signal processor running on a software defined radio platform. The processor enables reconfiguring important parameters of the physical layer during run-time in order to create a multitude of modern waveforms. Thirdly, by introducing a generic test infrastructure, which can be tailored to prototype diverse wireless technology and which is remotely accessible in order to invite new ideas by third parties. Using the test infrastructure, the performance of the flexible transceiver is evaluated regarding latency, achievable throughput and packet error rates.:List of figures List of tables Abbreviations Notations 1 Introduction 1.1 Wireless applications 1.2 Motivation 1.3 Software-Defined Radio 1.4 State of the art 1.5 Testbed 1.6 Summary 2 Background 2.1 System Model 2.2 PHY Layer Structure 2.3 Generalized Frequency Division Multiplexing 2.4 Wireless Standards 2.4.1 IEEE 802.15.4 2.4.2 802.11 WLAN 2.4.3 LTE 2.4.4 Low Latency Industrial Wireless Communications 2.4.5 Summary 3 Wireless Prototyping 3.1 Testbed Examples 3.1.1 PHY - focused Testbeds 3.1.2 MAC - focused Testbeds 3.1.3 Network - focused testbeds 3.1.4 Generic testbeds 3.2 Considerations 3.3 Use cases and Scenarios 3.4 Requirements 3.5 Methodology 3.6 Hardware Platform 3.6.1 Host 3.6.2 FPGA 3.6.3 Hybrid 3.6.4 ASIC 3.7 Software Platform 3.7.1 Testbed Management Frameworks 3.7.2 Development Frameworks 3.7.3 Software Implementations 3.8 Deployment 3.9 Discussion 3.10 Conclusion 4 Flexible Transceiver 4.1 Signal Processing Modules 4.1.1 MAC interface 4.1.2 Encoding and Mapping 4.1.3 Modem 4.1.4 Post modem processing 4.1.5 Synchronization 4.1.6 Channel Estimation and Equalization 4.1.7 Demapping 4.1.8 Flexible Configuration 4.2 Analysis 4.2.1 Numerical Precision 4.2.2 Spectral analysis 4.2.3 Latency 4.2.4 Resource Consumption 4.3 Discussion 4.3.1 Extension to MIMO 4.4 Summary 5 Testbed 5.1 Infrastructure 5.2 Automation 5.3 Software Defined Radio Platform 5.4 Radio Frequency Front-end 5.4.1 Sub 6 GHz front-end 5.4.2 26 GHz mmWave front-end 5.5 Performance evaluation 5.6 Summary 6 Experiments 6.1 Single Link 6.1.1 Infrastructure 6.1.2 Single Link Experiments 6.1.3 End-to-End 6.2 Multi-User 6.3 26 GHz mmWave experimentation 6.4 Summary 7 Key lessons 7.1 Limitations Experienced During Development 7.2 Prototyping Future 7.3 Open points 7.4 Workflow 7.5 Summary 8 Conclusions 8.1 Future Work 8.1.1 Prototyping Workflow 8.1.2 Flexible Transceiver Core 8.1.3 Experimental Data-sets 8.1.4 Evolved Access Point Prototype For Industrial Networks 8.1.5 Testbed Standardization A Additional Resources A.1 Fourier Transform Blocks A.2 Resource Consumption A.3 Channel Sounding using Chirp sequences A.3.1 SNR Estimation A.3.2 Channel Estimation A.4 Hardware part lis

Development And Implementation Of A New Technique For Bert (Bit Error Rate Tester) Using SDR Platform

Hardware/Software (HW/SW) co-design approaches become prospective choice due to its real time operation since these solutions are so flexible that cover extensive complicated systems and reduce time from design to market. Hybrid digital signal processors (DSPs), field programmable gate arrays (FPGAs) and general-purpose processors (GPPs) designs are viable solution for software defined radio (SDR) technology. This thesis demonstrates a practical design and implementation procedure for building a useful, efficient and flexible model of a bit error rate tester (BERT) on physical layer for UHF-band of the digital transceivers by using new architecture in Multi-Core Software-Defined Radi