A direct-execution parallel architecture for the Advanced Continuous Simulation Language (ACSL)

A direct-execution parallel architecture for the Advanced Continuous Simulation Language (ACSL) is presented which overcomes the traditional disadvantages of simulations executed on a digital computer. The incorporation of parallel processing allows the mapping of simulations into a digital computer to be done in the same inherently parallel manner as they are currently mapped onto an analog computer. The direct-execution format maximizes the efficiency of the executed code since the need for a high level language compiler is eliminated. Resolution is greatly increased over that which is available with an analog computer without the sacrifice in execution speed normally expected with digitial computer simulations. Although this report covers all aspects of the new architecture, key emphasis is placed on the processing element configuration and the microprogramming of the ACLS constructs. The execution times for all ACLS constructs are computed using a model of a processing element based on the AMD 29000 CPU and the AMD 29027 FPU. The increase in execution speed provided by parallel processing is exemplified by comparing the derived execution times of two ACSL programs with the execution times for the same programs executed on a similar sequential architecture

Study of Various Motherboards

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Maximizing resource utilization by slicing of superscalar architecture

Superscalar architectural techniques increase instruction throughput from one instruction per cycle to more than one instruction per cycle. Modern processors make use of several processing resources to achieve this kind of throughput. Control units perform various functions to minimize stalls and to ensure a continuous feed of instructions to execution units. It is vital to ensure that instructions ready for execution do not encounter a bottleneck in the execution stage; This thesis work proposes a dynamic scheme to increase efficiency of execution stage by a methodology called block slicing. Implementing this concept in a wide, superscalar pipelined architecture introduces minimal additional hardware and delay in the pipeline. The hardware required for the implementation of the proposed scheme is designed and assessed in terms of cost and delay. Performance measures of speed-up, throughput and efficiency have been evaluated for the resulting pipeline and analyzed

DESIGN SPACE EXPLORATION AND OPTIMIZATION OF SUPER SCALAR PROCESSOR

Designing a microprocessor involves determining the optimal microarchitecture for a given objective function and a given set of constraints. Superscalar processing is the latest in along series of innovations aimed at producing ever-faster microprocessors. By exploiting instruction-level parallelism, superscalar processors[1] are capable of executing more than one instruction in a clock cycle.The architectural design of super scalar processor involves a lot of trade off issues when selecting parameter values for instruction level parallelism.The use of critical quantitative analysis based upon the Simple Scalar simulations is necessary to select optimal parameter values for the processor aimed at specific target environment. This paper aims at finding optimal values for the super scalar processor and determines which processor parameters have the greatest impact on the simulated execution time

An assessment of aspects of the ecological status of the Klip River

Abstract : The degradation of aquatic resources has become an issue of great concern to authorities, interested and affected members of the public. Management actions implemented throughout the years for sustainable water use have failed and the ongoing impacts of anthropogenic activities can be reflected in the deterioration of aquatic ecosystems. The impacts of the physical and chemical alterations occurring in rivers can be integrated and reflected by the aquatic communities such as macro invertebrates, fish and riparian vegetation. The main aim of the study was to determine the current ecological state of the Klip River by measuring selected water quality variables; conduct an integrated habitat assessment and assess macro-invertebrate communities as ecological indicators. Six sites (K1-K6) were selected along the Klip River, upstream and downstream of identified point sources of pollution. The in situ water quality parameters measured included temperature, pH, and electrical conductivity as well as dissolved oxygen. Nutrient and metal concentrations were also measured at all study sites. The aquatic macroinvertebrate monitoring was conducted using the South African Scoring System version 5 (SASS5) and the assessment of habitat quality was conducted using the Integrated Habitat Assessment System (IHAS). The results from the study indicated the water quality to be poor as the concentration levels of all parameters from study site K1 to K6 exceeded the target water quality range (TWQR) for aquatic ecosystems. Site K1, at the source of the Klip River, recorded the highest levels of silver, iron, nickel and manganese and the levels of phosphate, chlorophyll-a, free and saline ammonia increased from K2 to K6 downstream of the waste water treatment works. The ecological classes for the macro-invertebrates from sites K1 to K6 were all in the category class E/F indicative of a critically modified state with low species diversity and the absence on sensitive species at all sites. This was also indicated by the low average score per taxa (ASPT) and SASS5 scores recorded at all sites. The habitat quality was only adequate at the upstream site K1 and in a poor, unacceptable state at sites K2 to K6. The principal component analysis (PCA) showed that sites K4 & K5 grouped together with DO, EC, pH. Chlorophyll-a, Total Phosphates, Nitrites and Nitrates grouped with sites K2 and K3. The PCA for metals and sampling sites indicated a grouping for Cobalt, Silver, Nickel and Iron with site K1. The metals Magnesium, Phosphorus, Boron, Silicon, Barium and Aluminium showed a grouping with site K6 and Potassium, Calcium and Sodium with sites K2 and K5. Site K1 grouped with the macro-invertebrates Culicidae and Amphipoda. Sites K3 and K6 grouped with the macro-invertebrate families Gerridae, Gyrinidae and Coenagrionidae. Sites K2 and K5 showed an association with macro-invertebrate families Baetidae, Gomphidae, Notonectidae, Dytisdae, Hydropsychidae and Belostomatidae. More of the families were recorded at sites below waste water treatment works (K2 & K5) and few families were recorded upstream at site K1.M.Sc. (Aquatic Health

Using Rapid Prototyping in Computer Architecture Design Laboratories

This paper describes the undergraduate computer architecture courses and laboratories introduced at Georgia Tech during the past two years. A core sequence of six required courses for computer engineering students has been developed. In this paper, emphasis is placed upon the new core laboratories which utilize commercial CAD tools, FPGAs, hardware emulators, and a VHDL based rapid prototyping approach to simulate, synthesize, and implement prototype computer hardware

Performance Comparison of Static CMOS and Domino Logic Style in VLSI Design: A Review

Of late, there is a steep rise in the usage of handheld gadgets and high speed applications. VLSI designers often choose static CMOS logic style for low power applications. This logic style provides low power dissipation and is free from signal noise integrity issues. However, designs based on this logic style often are slow and cannot be used in high performance circuits. On the other hand designs based on Domino logic style yield high performance and occupy less area. Yet, they have more power dissipation compared to their static CMOS counterparts. As a practice, designers during circuit synthesis, mix more than one logic style judiciously to obtain the advantages of each logic style. Carefully designing a mixed static Domino CMOS circuit can tap the advantages of both static and Domino logic styles overcoming their own short comings