Asymptotic Methods for Metal Oxide Semiconductor Field Effect Transistor Modeling

The behavior of metal oxide semiconductor field effect transistors (MOSFETs) with small aspect ratio and large doping levels is analyzed using formal perturbation techniques. Specifically, the influence of interface layers in the potential on the averaged channel conductivity is closely examined. The interface and internal layers that occur in the potential are resolved in the limit of large doping using the method of matched asymptotic expansions. This approach, together with other asymptotic techniques, provides both a pointwise description of the state variables as well as lumped current-voltage relations that vary uniformly across the various bias regimes. These current-voltage relations are derived for a variable doping model respresenting a particular class of devices

High intensity study of THz detectors based on field effect transistors

Terahertz power dependence of the photoresponse of field effect transistors, operating at frequencies from 0.1 to 3 THz for incident radiation power density up to 100 kW/cm^2 was studied for Si metal-oxide-semiconductor field-effect transistors and InGaAs high electron mobility transistors. The photoresponse increased linearly with increasing radiation power up to kW/cm^2 range. The saturation of the photoresponse was observed for all investigated field effect transistors for intensities above several kW/cm^2. The observed signal saturation is explained by drain photocurrent saturation similar to saturation in direct currents output characteristics. The theoretical model of terahertz field effect transistor photoresponse at high intensity was developed. The model explains quantitatively experimental data both in linear and nonlinear (saturation) range. Our results show that dynamic range of field effect transistors is very high and can extend over more than six orderd of magnitudes of power densities (from 0.5 mW/cm^2 to 5 kW/cm^2)

The 'gated-diode' configuration in MOSFET's, a sensitive tool for characterizing hot-carrier degradation

This paper describes a new measurement technique, the forward gated-diode current characterized at low drain voltages to be applied in MOSFET's for investigating hot-carrier stress-induced defects at high spatial resolution. The generation/recombination current in the drain-to-substrate diode as a function of gate voltage, combined with two-dimensional numerical simulation, provides a sensitive tool for detecting the spatial distribution and density of interface defects. In the case of strong accumulation, additional information is obtained from interband tunneling processes occurring via interface defects. The various mechanisms for generating interface defects and fixed charges at variable stress conditions are discussed, showing that information complementary to that available from other methods is obtaine

Metallicity and its low temperature behavior in dilute 2D carrier systems

We theoretically consider the temperature and density dependent transport properties of semiconductor-based 2D carrier systems within the RPA-Boltzmann transport theory, taking into account realistic screened charged impurity scattering in the semiconductor. We derive a leading behavior in the transport property, which is exact in the strict 2D approximation and provides a zeroth order explanation for the strength of metallicity in various 2D carrier systems. By carefully comparing the calculated full nonlinear temperature dependence of electronic resistivity at low temperatures with the corresponding asymptotic analytic form obtained in the $T/T_F \to 0$ limit, both within the RPA screened charged impurity scattering theory, we critically discuss the applicability of the linear temperature dependent correction to the low temperature resistivity in 2D semiconductor structures. We find quite generally that for charged ionized impurity scattering screened by the electronic dielectric function (within RPA or its suitable generalizations including local field corrections), the resistivity obeys the asymptotic linear form only in the extreme low temperature limit of $T/T_F \le 0.05$. We point out the experimental implications of our findings and discuss in the context of the screening theory the relative strengths of metallicity in different 2D systems.Comment: We have substantially revised this paper by adding new materials and figures including a detailed comparison to a recent experimen

Operational Amplifier Design in CMOS at Low-Voltage for Sensor Input Front-End Circuits in VLSI Devices

Today, digital circuit cores provide the main circuit implementation approach for integrated circuit (IC) functions in very-large-scale integration (VLSI) circuits and systems. Typical functions include sensor signal input, data storage, digital signal processing (DSP) operations, system control and communications. Despite the fact that a large portion of the circuitry may be developed and implemented using digital logic techniques, there is still a need for high performance analogue circuits such as amplifiers and filters that provide signal conditioning functionality prior to sampling into the digital domain using an analogue-to-digital converter (ADC) for analogue sensor signals. The demands on the design require a multitude of requirements to be taken into account. In this chapter, the design of the operational amplifier (op-amp) is discussed as an important circuit within the front-end circuitry of a mixed-signal IC. The discussion will focus on the design of the op-amp using different compensation schemes incorporating negative Miller compensation and designed to operate at lower power supply voltage levels. A design case study is included which utilises the g m /I D ratio design approach to determine the transistor sizes. The simulation approach is focussed on the open-loop frequency response performance of the op-amp

MOSFET ZTC condition analysis for a self-biased current reference design

In this paper a self-biased current reference based on Metal-Oxide-Semiconductor Field Effect Transistor (MOSFET) Zero Temperature Coefficient (ZTC) condition is proposed. It can be imple mented in any Complementary Metal-Oxide-Semiconductor (CMOS) fabrication process and pro vides another alternative to design current references. In order to support the circuit design, ZTC condition is analyzed using a MOSFET model that is continuous from weak to strong inversion, show ing that this condition always occurs from moderate to strong inversion in any CMOS process. The proposed topology was designed in a 180 nm process, operates with a supply voltage from 1.4V to 1.8 V and occupies around 0.010mm2 of silicon area. From circuit simulations our reference showed a temperature coefficient (TC) of 15 ppm/o C from -40 to +85o C, and a fabrication process sensitivity of σ/μ = 4.5% for the current reference, including average process and local mismatch variability analysis. The simulated power supply sensitivity is estimated around 1%/V

Ultra Low Power Design for Digital CMOS Circuits Operating Near Threshold

Circuits operating in the subthreshold region are synonymous to low energy operation. However, the penalty in performance is colossal. In this paper, we investigate how designing in moderate inversion region recuperates some of that lost performance, while remaining very near to the minimum energy point. An power based minimum energy delay modeling that is continuous over the weak, moderate, and strong inversion regions is presented. The effect of supply voltage and device sizing on the minimum energy and performance is determined. The proposed model is utilized to design a temperature to time generator at 32nm technology node asthe application of the proposed model

Diffusive Transport in Quasi-2D and Quasi-1D Electron Systems

Quantum-confined semiconductor structures are the cornerstone of modern-day electronics. Spatial confinement in these structures leads to formation of discrete low-dimensional subbands. At room temperature, carriers transfer among different states due to efficient scattering with phonons, charged impurities, surface roughness and other electrons, so transport is scattering-limited (diffusive) and well described by the Boltzmann transport equation. In this review, we present the theoretical framework used for the description and simulation of diffusive electron transport in quasi-two-dimensional and quasi-one-dimensional semiconductor structures. Transport in silicon MOSFETs and nanowires is presented in detail.Comment: Review article, to appear in Journal of Computational and Theoretical Nanoscienc