An addition to the methods of test determination for fault detection in combinational circuits

We propose a procedure for determining fault detection tests for single and multiple fault in combinational circuits. The stuck-at-fault model is used. By the proposed procedure all test vectors for single and multiple stuck-at-fault in combinational circuit are determined. The path sensitization method is used in the test signal propagation while test signals are defined on a four element set. The procedure can also be applied to the fault detection in programmable logic devices. We consider two-level combinational circuits which are realized by the PAL architecture and we propose a procedure for determining a test set which detects all single stuck-at-faults. As a mathematical tool, the cube theory is used

FACTPLA: Functional analysis and the complexity of testing programmable logic array

This thesis was submitted for the degree of Doctor of Philosophy and awarded by Brunel University.A computer aided method for analyzing the testability of Programmable Logic Arrays (PLAs) is described. The method, which is based on a functional verification approach, estimates the complexity of testing a PLA according to the amount of single undetectable faults in the array structure. An analytic program (FACTPLA) is developed to predict the above complexity without analyzing the topology of the array as such. Thus, the method is technology invariant and depends only on the functionality of the PLA. The program quantitatively evaluates the effects of undetectable faults and produces some testability measures to manifest these effects. A testability profile for different PLA examples is provided and a number of suggestions for further research to establish definitely the usefulness of some functional properties for testing were made

The effectiveness of different test sets for PLAs

It has been theoretically demonstrated that the single stuck-at fault model for a PLA does not cover as many faults as the single crosspoint model. What has not been demonstrated is the real relative effectiveness of test sets generated using these models. This paper presents the results of a study involving presenting a number of test sets to fabricated PLAs to determine their effectiveness. The test sets included weighted random patterns, of particular interest owing to PLAs being random resistant. Details are given of a method to generate weights, taking into account a PLA's structure

A survey of fault-tolerance algorithms for reconfigurable nano-crossbar arrays

ACM Comput. Surv. Volume 50, issue 6 (November 2017)Nano-crossbar arrays have emerged as a promising and viable technology to improve computing performance of electronic circuits beyond the limits of current CMOS. Arrays offer both structural efficiency with reconfiguration and prospective capability of integration with different technologies. However, certain problems need to be addressed, and the most important one is the prevailing occurrence of faults. Considering fault rate projections as high as 20% that is much higher than those of CMOS, it is fair to expect sophisticated fault-tolerance methods. The focus of this survey article is the assessment and evaluation of these methods and related algorithms applied in logic mapping and configuration processes. As a start, we concisely explain reconfigurable nano-crossbar arrays with their fault characteristics and models. Following that, we demonstrate configuration techniques of the arrays in the presence of permanent faults and elaborate on two main fault-tolerance methodologies, namely defect-unaware and defect-aware approaches, with a short review on advantages and disadvantages. For both methodologies, we present detailed experimental results of related algorithms regarding their strengths and weaknesses with a comprehensive yield, success rate and runtime analysis. Next, we overview fault-tolerance approaches for transient faults. As a conclusion, we overview the proposed algorithms with future directions and upcoming challenges.This work is supported by the EU-H2020-RISE project NANOxCOMP no 691178 and the TUBITAK-Career project no 113E760

Fault Tolerant Nano-Memory with Fault Secure Encoder and Decoder

We introduce a nanowire-based, sublithographic memory architecture tolerant to transient faults. Both the storage elements and the supporting ECC encoder and corrector are implemented in dense, but potentially unreliable, nanowirebased technology. This compactness is made possible by a recently introduced Fault-Secure detector design [18]. Using Euclidean Geometry error-correcting codes (ECC), we identify particular codes which correct up to 8 errors in data words, achieving a FIT rate at or below one for the entire memory system for bit and nanowire transient failure rates as high as 10 −17 upsets/device/cycle with a total area below 1.7 × the area of the unprotected memory for memories as small as 0.1 Gbit. We explore scrubbing designs and show the overhead for serial error correction and periodic data scrubbing can be below 0.02 % for fault rates as high as 10 −20 upsets/device/cycle. We also present a design to unify the error-correction coding and circuitry used for permanent defect and transient fault tolerance

Test Procedure for Erasable Programmable Logic Devices

This study was begun to fulfill part of contract number 01-3374 with Sandia National Laboratories in Sandia, New Mexico. A report of the entire projectentitled "Sandia Sea Lance Telemetry Testing" was submitted to Sandia National Laboratories in January, 1987.Electrical Engineerin