111 research outputs found
Quantum cost efficient reversible . . .
Reversible logic allows low power dissipating circuit design and founds its application in cryptography, digital signal processing, quantum and optical information processing. This paper presents a novel quantum cost efficient reversible BCD adder for nanotechnology based systems using PFAG gate. It has been demonstrated that the proposed design offers less hardware complexity and requires minimum number of garbage outputs than the existing counterparts. The remarkable property of the proposed designs is that its quantum realization is given in NMR technology
Reversible Logic Synthesis of Fault Tolerant Carry Skip BCD Adder
Reversible logic is emerging as an important research area having its
application in diverse fields such as low power CMOS design, digital signal
processing, cryptography, quantum computing and optical information processing.
This paper presents a new 4*4 parity preserving reversible logic gate, IG. The
proposed parity preserving reversible gate can be used to synthesize any
arbitrary Boolean function. It allows any fault that affects no more than a
single signal readily detectable at the circuit's primary outputs. It is shown
that a fault tolerant reversible full adder circuit can be realized using only
two IGs. The proposed fault tolerant full adder (FTFA) is used to design other
arithmetic logic circuits for which it is used as the fundamental building
block. It has also been demonstrated that the proposed design offers less
hardware complexity and is efficient in terms of gate count, garbage outputs
and constant inputs than the existing counterparts.Comment: 9 pages, 7 figures, 5 table
Low Power Reversible Parallel Binary Adder/Subtractor
In recent years, Reversible Logic is becoming more and more prominent
technology having its applications in Low Power CMOS, Quantum Computing,
Nanotechnology, and Optical Computing. Reversibility plays an important role
when energy efficient computations are considered. In this paper, Reversible
eight-bit Parallel Binary Adder/Subtractor with Design I, Design II and Design
III are proposed. In all the three design approaches, the full Adder and
Subtractors are realized in a single unit as compared to only full Subtractor
in the existing design. The performance analysis is verified using number
reversible gates, Garbage input/outputs and Quantum Cost. It is observed that
Reversible eight-bit Parallel Binary Adder/Subtractor with Design III is
efficient compared to Design I, Design II and existing design.Comment: 12 pages,VLSICS Journa
A review on reversible logic gates
In recent years, reversible logic circuits have applications in the emerging field of digital signal processing, optical information processing, quantum computing and nano technology. Reversibility plays an important role when computations with minimal energy dissipation are considered. The main purpose of designing reversible logic is to decrease the number of reversible gates, garbage outputs, constant inputs, quantum cost, area, power, delay and hardware complexity of the reversible circuits. This paper reveals a comparative review on various reversible logic gates. This paper provides some reversible logic gates, which can be used in designing more complex systems having reversible circuits and can execute more complicated operations using quantum computers. Future digital technology will use reversible logic gates in order to reduce the power consumption and propagation delay as it effectively provides negligible loss of information in the circuit.
Keywords: Garbage output, Power dissipation, quantum cost, Reversible Gate, Reversible logic
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