Use of frequency response masking technique in designing A/D converter for SDR.

Thesis (M.Sc.Eng.)-University of KwaZulu-Natal, Durban, 2005.Analog-to-digital converters (ADCs) are required in almost all signal processing and communication systems. They are often the most critical components, since they tend to determine the overall system performance. Hence, it is important to determine their performance limitations and develop improved realizations. One of the most challenging tasks for realizing software defined radio (SDR) is to move ND conversion as close to the antenna as possible, this implies that the ADC has to sample the incoming signal with a very high sample rate (over 100 MSample/s) and with a very high resolution (14 -to -16 bits). To design and implement AID converters with such high performance, it is necessary to investigate new designing techniques. The focus in this work is on a particular type of potentially high-performance (high-resolution and highspeed) analog-to-digital conversion technique, utilizing filter banks, where two or more ADCs are used in the converter array in parallel together with asymmetric filter banks. The hybrid filter bank analog-todigital converter (HFB ADC) utilizes analog filters (analysis filters) to allocate a frequency band to each ADC in a converter array and digital synthesis filters to reconstruct the digitized signal. The HFB improves the speed and resolution of the conversion, in comparison to the standard time-interleaving technique by attenuating the effect of gain and phase mismatches between the ADCs. Many of the designs available in the literature are compromising between some metrics: design complexity, order of the filter bank (computation time) and the sharpness of the frequency response rolloff (the transition from the pass band to the stop band). In this dissertation, five different classes of near perfect magnitude reconstruction (NPMR) continuoustime hybrid filter banks (CT HFBs) are proposed. In each of the five cases, two filter banks are designed; analysis filter bank and synthesis filter bank. Since the systems are hybrid, continuous time IlR filter are used to implement the analysis filter bank and digital filters are used for the synthesis filter bank. To optimize the system, we used a new technique, known in the literature as frequency response masking (FRM), to design the synthesis filter bank. In this technique, the sharp roll-off characteristics can be achieved while keeping the complexity of the filter within practical range, this is done by splitting the filter into two filters in cascade; model filter with relaxed roll-off characteristics followed by a masking filter. One of the main factors controlling the overall complexity of the filter is the way of designing the model filter and that of designing the masking filter. The dissertation proposes three combinations: use of HR model filter and IlR masking filter, HR model filter/FIR masking filter and FIR model filter/FIR masking filter. To show the advantages of our designs, we considered the cases of designing the synthesis filter as one filter, either FIR or IlR. These two filters are used as base for comparison with our proposed designs (the use of masking response filter). The results showed the following: 1. Asymmetric hybrid filter banks alone are not sufficient for filters with sharp frequency response roll-off especially for HR/FIR class. 2. All classes that utilize FRM in their synthesis filter banks gave a good performance in general in comparison to conventional classes, such as the reduction of the order of filters 3. HR/HR FRM gave better performance than HR/FIR FRM. 4. Comparing HR/HR FRM using FIR masking filters and HR/IIR FRM using IIR masking filters, the latter gave better performance (the performance is generally measured in terms of reduced filter order). 5. All classes that use the FRM approach have a very low complexity, in terms of reduced filter order. Our target was to design a system with the following overall characteristics: pass band ripple of -0.01 dB, stop band minimum attenuation of - 40 dB and of response roll-off of 0.002. Our calculations showed that the order of the conventional IIR/FIR filter that achieves such characteristics is aboutN =2000. Using the FRM technique, the order N reduced to aboutN = 244, N = 179 for IIRJFIR and IIR/IIR classes, respectively. This shows that the technique is very effective in reducing the filter complexity. 6. The magnitude distortion and the aliasing noise are calculated for each design proposal and compared with the theoretical values. The comparisons show that all our proposals result in approximately perfect magnitude reconstruction (NPMR). In conclusion, our proposal of using frequency-response masking technique to design the synthesis filter bank can, to large extent, reduce the complexity of the system. The design of the system as a whole is simplified by designing the synthesis filter bank separately from the design of the analysis filter bank. In this case each bank is optimized separately. This implies that for SDR applications we are proposing the use of the continuous-time HFB ADC (CT HFB ADC) structure utilizing FRM for digital filters

Design of a 3 GHz fine resolution LC DCO

In this thesis, the design of a fine resolution LC digitally controlled oscillator (DCO) is introduced. Two NMOS varactor banks are used to achieve 12 bits medium and fine frequency tuning. Both delta-sigma modulator and capacitive divider circuit are implemented to achieve a finer resolution and a larger dynamic range. The LC-oscillator has a coarse tuning range from 3.05 GHz to 3.85 GHz and a fine tuning range of 50MHz. It features a phase noise level of -115dBc/Hz at 1MHz frequency offset and consumes 5.4mW. Efficient simulation methodology is explored. Finally, this DCO is simulated in an All-Digital Phase Locked Loop (ADPLL) with other ideal behavior blocks implemented using Verilog-A, and the performance of the DCO is evaluated.Electrical and Computer Engineerin

Anti-aliasing Filter in Hybrid Filter Banks

International audienceHybrid Filter Banks allow wide-band, high frequency conversion. All existing design methods suppose that the input signal is band-limited and that each sub-band signal is sampled at 1/M times the effective Nyquist frequency of the input signal 1/T . To avoid aliasing in the sampling process, an analog anti-aliasing filter should be used in order to eliminate noise in frequency bands in which there is no signal (or a few signal) . In this paper, it is shown that this pre-filtering operation is critical and has to be done taking into account the respective power spectral densities of signal and noise due to the spectral aliasing with the sampling rate compressor. Results will be demonstrated for the design of a realistic 8 channel Hybrid Filter Bank

Implementation of a Two-Channel Maximally Decimated Filter Bank using Switched Capacitor Circuits

The aim of this paper is to describe the implementation of a two-channel filter bank (FB) using the switched capacitor (SC) technique considering real properties of operational amplifiers (OpAmps). The design procedure is presented and key recommendations for the implementation are given. The implementation procedure describes the design of two-channel filter bank using an IIR Cauer filter, conversion of IIR into the SC filters and the final implementation of the SC filters. The whole design and an SC circuit implementation is performed by a PraCAn package in Maple. To verify the whole filter bank, resulting real property circuit structures are completely simulated by WinSpice and ELDO simulators. The results confirm that perfect reconstruction conditions can be almost accepted for the filter bank implemented by the SC circuits. The phase response of the SC filter bank is not strictly linear due to the IIR filters. However, the final ripple of a magnitude frequency response in the passband is almost constant, app. 0.5 dB for a real circuit analysis

Sensitivity of hybrid filter banks A/D converters to analog realization errors and finite word length

This paper studies the sensitivity of hybrid filter banks (HFB) to analog inaccuracies and finite word implementation. It is shown that very small errors affecting very simple analog structures have a dramatic influence on the performances of the HFB. The influence of the quantization of digital filter coefficients is also studied. A theoretical limit for the error introduced by the quantization of digital filter coefficients is derived

Hybrid Filter Bank A/D conversion systems applied to future telecommunication scenarios

Hybrid Filter Banks (HFB) A/D converters (ADC) are attractive to software-defined radio applications. Starting from a given sampling rate, they enlarge the conversion band-width. Also, it is possible to adapt the conversion characteristics (e.g. bandwidth and resolution) by software control. HFB have been studied in the context of the ANR VersaNum project. This work proposes optimal HFBs and a calibration technique to compensate the mismatch between the analog part and the digital part. Results are given for future telecommunication scenarios

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Principles of Neuromorphic Photonics

In an age overrun with information, the ability to process reams of data has become crucial. The demand for data will continue to grow as smart gadgets multiply and become increasingly integrated into our daily lives. Next-generation industries in artificial intelligence services and high-performance computing are so far supported by microelectronic platforms. These data-intensive enterprises rely on continual improvements in hardware. Their prospects are running up against a stark reality: conventional one-size-fits-all solutions offered by digital electronics can no longer satisfy this need, as Moore's law (exponential hardware scaling), interconnection density, and the von Neumann architecture reach their limits. With its superior speed and reconfigurability, analog photonics can provide some relief to these problems; however, complex applications of analog photonics have remained largely unexplored due to the absence of a robust photonic integration industry. Recently, the landscape for commercially-manufacturable photonic chips has been changing rapidly and now promises to achieve economies of scale previously enjoyed solely by microelectronics. The scientific community has set out to build bridges between the domains of photonic device physics and neural networks, giving rise to the field of \emph{neuromorphic photonics}. This article reviews the recent progress in integrated neuromorphic photonics. We provide an overview of neuromorphic computing, discuss the associated technology (microelectronic and photonic) platforms and compare their metric performance. We discuss photonic neural network approaches and challenges for integrated neuromorphic photonic processors while providing an in-depth description of photonic neurons and a candidate interconnection architecture. We conclude with a future outlook of neuro-inspired photonic processing.Comment: 28 pages, 19 figure

Wide-band multipath A to D converter for Cognitive Radio applications

This article presents a digital-enhanced radio frequency receiver for fast wide-band spectrum sensing. It is based on charge sampling and hybrid filter bank techniques. The charge sampling method is employed to design analog bandpass filters. Using a hybrid filter bank for wide-band analog-to-digital conversion improves the speed and resolution of the conversion. We propose to use these techniques in combination of frequencydivision multiplexing with time-division multiplexing to design an integrated, completely software reconfigurable and reliable backend of radio frequency receiver for cognitive radio applications