Design of pixel-level ADCs for energy-sensitive hybrid pixel detectors

Single-photon counting hybrid pixel detectors have shown\ud to be a valid alternative to other types of X-ray imaging\ud devices due to their high sensitivity, low noise, linear behavior\ud and wide dynamic range. One important advantage of these\ud devices is the fact that detector and readout electronics are\ud manufactured separately. This allows the use of industrial\ud state-of-the-art CMOS processes to make the readout\ud electronics, combined with a free choice of detector material\ud (high resistivity Silicon, GaAs or other). By measuring not\ud only the number of X-ray photons but also their energies (or\ud wavelengths), the information content of the image increases,\ud given the same X-ray dose. We have studied several\ud possibilities of adding energy sensitivity to the single photon\ud counting capability of hybrid pixel detectors, by means of\ud pixel-level analog-to-digital converters. We show the results of\ud simulating different kinds of analog-to-digital converters in\ud terms of power, area and speed

Simulation-based high-level synthesis of Nyquist-rate data converters using MATLAB/SIMULINK

This paper presents a toolbox for the simulation, optimization and high-level synthesis of Nyquist-rate Analog-to-Digital (A/D) and Digital-to-Analog (D/A) Converters in MATLAB®. The embedded simulator uses SIMULINK® C-coded S-functions to model all required subcircuits including their main error mechanisms. This approach allows to drastically speed up the simulation CPU-time up to 2 orders of magnitude as compared with previous approaches - based on the use of SIMULINK® elementary blocks. Moreover, S-functions are more suitable for implementing a more detailed description of the circuit. For all subcircuits, the accuracy of the behavioral models has been verified by electrical simulation using HSPICE. For synthesis purposes, the simulator is used for performance evaluation and combined with an hybrid optimizer for design parameter selection. The optimizer combines adaptive statistical optimization algorithm inspired in simulated annealing with a design-oriented formulation of the cost function. It has been integrated in the MATLAB/SIMULINK® platform by using the MATLAB® engine library, so that the optimization core runs in background while MATLAB® acts as a computation engine. The implementation on the MATLAB® platform brings numerous advantages in terms of signal processing, high flexibility for tool expansion and simulation with other electronic subsystems. Additionally, the presented toolbox comprises a friendly graphical user interface to allow the designer to browse through all steps of the simulation, synthesis and post-processing of results. In order to illustrate the capabilities of the toolbox, a 0.13)im CMOS 12bit@80MS/s analog front-end for broadband power line communications, made up of a pipeline ADC and a current steering DAC, is synthesized and high-level sized. Different experiments show the effectiveness of the proposed methodology.Ministerio de Ciencia y Tecnología TIC2003-02355RAICONI

Design techniques for low-power multi-GS/s analog-to-digital converters

Ultra-high-speed (>10GS/s), medium-resolution (5~6bit), low-power (<50mW) analog-to-digital converter can find it application in the areas of digital oscilloscopes and next-generation serial link receivers. There are several challenges to enable a successful design, however. First, the time-interleaved architecture is required in order to achieve over 10GS/s sampling rate, with the trade-off of the number of the channels and the sampling rate in each channel. Phase misalignment and channel mismatch must be considered too. Second, timing accuracy, especially dynamic jitter of sampling clock becomes a major concern at ultra-high frequency, and certain techniques must be taken to address it. Finally, to achieve low power consumption, Flash architecture is not suitable to serve as the sub-ADC, and a low-power sub-ADC that can work at relatively high speed need to be designed. A single channel, asynchronous successive approximation (SA) ADC with improved feedback delay has been fabricated in 40nm CMOS. Compared with a conventional SA structure that employs a single quantizer controlled by a digital feedback logic loop, the proposed SA-ADC employs multiple quantizers for each conversion bit, clocked by an asynchronous ripple clock that is generated after each quantization. Hence, the sampling rate of the 6-bit ADC is limited only by the six delays of the Capacitive-DAC settling and each comparator’s quantization delay, as the digital logic delay is eliminated. Measurement results of the 40nm-CMOS SA-ADC achieves peak SNDR of 32.9dB at 1GS/s and 30.5dB at 1.25GS/s, consuming 5.28mW and 6.08mW respectively, leading to FoM of 148fJ/conversion-step and 178fJ/conversion-step, in a core area less than 170µm by 85µm. Based on the previous work of sub-ADC, a 12-GS/s 5-b 50-mW ADC is designed in 40nm CMOS with 8 time-interleaved channels of Flash-SA hybrid structure each running at 1.5GS/s. A modified bootstrapped switch is used in the track-and-hold circuit, introducing a global clock signal to synchronize the sampling instants of each individual channel, therefore improve the phase alignment and reduce distortion. The global clock is provided by a CML buffer which is injected by off-chip low-noise sine-wave signal, so that the RMS dynamic jitter is low for better ENOB performance. Measurement results show that the 12GS/s ADC can achieve a SNDR of 25.8dB with the input signal frequency around DC and 22.8dB around 2GHz, consuming 32.1mW, leading to FoM of 237.3fJ/conversion-step, in a core area less than 800µm by 500µm

Noise shaping Asynchronous SAR ADC based time to digital converter

Time-to-digital converters (TDCs) are key elements for the digitization of timing information in modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring circuits. Especially, high-resolution TDCs are increasingly employed in on-chip timing tests, such as jitter and clock skew measurements, as advanced fabrication technologies allow fine on-chip time resolutions. Its main purpose is to quantize the time interval of a pulse signal or the time interval between the rising edges of two clock signals. Similarly to ADCs, the performance of TDCs are also primarily characterized by Resolution, Sampling Rate, FOM, SNDR, Dynamic Range and DNL/INL. This work proposes and demonstrates 2nd order noise shaping Asynchronous SAR ADC based TDC architecture with highest resolution of 0.25 ps among current state of art designs with respect to post-layout simulation results. This circuit is a combination of low power/High Resolution 2nd Order Noise Shaped Asynchronous SAR ADC backend with simple Time to Amplitude converter (TAC) front-end and is implemented in 40nm CMOS technology. Additionally, special emphasis is given on the discussion on various current state of art TDC architectures.Electrical and Computer Engineerin

Performance of prototype BTeV silicon pixel detectors in a high energy pion beam

The silicon pixel vertex detector is a key element of the BTeV spectrometer. Sensors bump-bonded to prototype front-end devices were tested in a high energy pion beam at Fermilab. The spatial resolution and occupancies as a function of the pion incident angle were measured for various sensor-readout combinations. The data are compared with predictions from our Monte Carlo simulation and very good agreement is found.Comment: 24 pages, 20 figure

Low Power Analog-to-Digital Conversion in Millimeter Wave Systems: Impact of Resolution and Bandwidth on Performance

The wide bandwidth and large number of antennas used in millimeter wave systems put a heavy burden on the power consumption at the receiver. In this paper, using an additive quantization noise model, the effect of analog-digital conversion (ADC) resolution and bandwidth on the achievable rate is investigated for a multi-antenna system under a receiver power constraint. Two receiver architectures, analog and digital combining, are compared in terms of performance. Results demonstrate that: (i) For both analog and digital combining, there is a maximum bandwidth beyond which the achievable rate decreases; (ii) Depending on the operating regime of the system, analog combiner may have higher rate but digital combining uses less bandwidth when only ADC power consumption is considered, (iii) digital combining may have higher rate when power consumption of all the components in the receiver front-end are taken into account.Comment: 8 pages, 6 figures, in Proc. of IEEE Information Theory and Applications Workshop, Feb. 201

5G Millimeter Wave Cellular System Capacity with Fully Digital Beamforming

Due to heavy reliance of millimeter-wave (mmWave) wireless systems on directional links, Beamforming (BF) with high-dimensional arrays is essential for cellular systems in these frequencies. How to perform the array processing in a power efficient manner is a fundamental challenge. Analog and hybrid BF require fewer analog-to-digital converters (ADCs), but can only communicate in a small number of directions at a time,limiting directional search, spatial multiplexing and control signaling. Digital BF enables flexible spatial processing, but must be operated at a low quantization resolution to stay within reasonable power levels. This paper presents a simple additive white Gaussian noise (AWGN) model to assess the effect of low resolution quantization of cellular system capacity. Simulations with this model reveal that at moderate resolutions (3-4 bits per ADC), there is negligible loss in downlink cellular capacity from quantization. In essence, the low-resolution ADCs limit the high SNR, where cellular systems typically do not operate. The findings suggest that low-resolution fully digital BF architectures can be power efficient, offer greatly enhanced control plane functionality and comparable data plane performance to analog BF.Comment: To appear in the Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 201

Designs and calibration of delay-line based ADCs

Delay line ADCs become more and more attractive with technology scaling to smaller dimensions with lower voltages. Time domain resolution can be increased by high speed delay cells. A GHz sampling rate can be easily achieved with low power. However, linearity, which has always been an issue, becomes a problem with longer delay lines. Resolutions of reported delay-line ADCs are hardly more than 4 bits with sampling rates of hundreds of MHz. Thus, this dissertation addresses the linearity issue of delay line ADCs. First, a novel 11-bit hybrid ADC using flash and delay line architectures, where a 4-bit flash ADC is followed by a 7-bit delay-line ADC, is proposed. In this structure, the noise/error of the second stage delay-line ADC is attenuated at the hybrid ADC output, such that the overall performance would not be limited by the poor linearity of the delay-line ADC. The achieved figure of merit (FOM) of 33.8 fJ/conversion-step is competitive with state-of-the-art ADCs. Furthermore, the proposed ADC inherits accuracy and high speed from the flash ADC and the delay-line ADC, respectively. The inherited advantages strongly support the scalability of the proposed ADC to provide a better performance with low power in further scaled fabrication processes. Second, in order to remove the harmonic distortion of delay-line ADC, we present a technique which extends harmonic distortion correction (HDC) to digitally calibrate a delay-line ADC. In our simulation results, digital calibration improves SNDR from 25.6 dB to 42.5 dB by averaging $2^{27}$ sample points, which corresponds to a 0.86 second calibration time. Last, a multiple-pass delay line ADC is proposed to improve overall ADC performance in terms of speed and resolution. In this structure, a multiple-pass delay cell can be early triggered by the previous cell to increase speed. Also, phase interpolation is used to improve the effective number of bits. The design is designed and simulated in a commercial 40nm process technology. With 500MHz sampling rate, the multiple-pass delay line ADC achieves an SNDR of 37 dB and consumes 4.2 mW, which is competitive with other reported ADCs.Electrical and Computer Engineerin