Passive-performance, analysis, and upgrades of a 1-ton seismic attenuation system

The 10m Prototype facility at the Albert-Einstein-Institute (AEI) in Hanover, Germany, employs three large seismic attenuation systems to reduce mechanical motion. The AEI Seismic-Attenuation-System (AEI-SAS) uses mechanical anti-springs in order to achieve resonance frequencies below 0.5Hz. This system provides passive isolation from ground motion by a factor of about 400 in the horizontal direction at 4Hz and in the vertical direction at 9Hz. The presented isolation performance is measured under vacuum conditions using a combination of commercial and custom-made inertial sensors. Detailed analysis of this performance led to the design and implementation of tuned dampers to mitigate the effect of the unavoidable higher order modes of the system. These dampers reduce RMS motion substantially in the frequency range between 10 and 100Hz in 6 degrees of freedom. The results presented here demonstrate that the AEI-SAS provides substantial passive isolation at all the fundamental mirror-suspension resonances

Design and control of noise-induced synchronization patterns

We propose a method for controlling synchronization patterns of limit-cycle oscillators by common noisy inputs, i.e., by utilizing noise-induced synchronization. Various synchronization patterns, including fully synchronized and clustered states, can be realized by using linear filters that generate appropriate common noisy signals from given noise. The optimal linear filter can be determined from the linear phase response property of the oscillators and the power spectrum of the given noise. The validity of the proposed method is confirmed by numerical simulations.Comment: 6 pages, 4 figure

ElectroMagnetic Analysis and Fault Injection onto Secure Circuits

International audienceImplementation attacks are a major threat to hardware cryptographic implementations. These attacks exploit the correlation existing between the computed data and variables such as computation time, consumed power, and electromagnetic (EM) emissions. Recently, the EM channel has been proven as an effective passive and active attack technique against secure implementations. In this paper, we review the recent results obtained on this subject, with a particular focus on EM as a fault injection tool

Design and validation of a platform for electromagnetic fault injection

Security is acknowledged as one of the main challenges in the design and deployment of embedded circuits. Devices need to operate on-the-field safely and correctly, even when at physical reach of potential adversaries. One of the most powerful techniques to compromise the correct functioning of a device are fault injection attacks. They enable an active adversary to trigger errors on a circuit in order to bypass security features or to gain knowledge of security-sensitive information. There are several methods to induce such errors. In this work we focus on the injection of faults through the electromagnetic (EM) channel. In particular, we document our efforts towards building a suitable platform for EM pulse injection. We design a pulse injection circuit that can provide currents over 20 A to an EM injector in order to generate abrupt variations of the EM field on the vicinity of a circuit. We validate the suitability of our platform by applying a well-know attack on an embedded 8-bit microcontroller implementing the AES block cipher. In particular, we show how to extract the AES secret cryptographic keys stored in the device by careful injection of faults during the encryption operations and simple analysis of the erroneous outputs.Peer ReviewedPostprint (published version

CMOS Signal Synthesizers for Emerging RF-to-Optical Applications

The need for clean and powerful signal generation is ubiquitous, with applications spanning the spectrum from RF to mm-Wave, to into and beyond the terahertz-gap. RF applications including mobile telephony and microprocessors have effectively harnessed mixed-signal integration in CMOS to realize robust on-chip signal sources calibrated against adverse ambient conditions. Combined with low cost and high yield, the CMOS component of hand-held devices costs a few cents per part per million parts. This low cost, and integrated digital processing, make CMOS an attractive option for applications like high-resolution imaging and ranging, and the emerging 5-G communication space. RADAR techniques when expanded to optical frequencies can enable micrometers of resolution for 3D imaging. These applications, however, impose upto 100x more exacting specifications on power and spectral purity at much higher frequencies than conventional RF synthesizers. This generation of applications will present unconventional challenges for transistor technologies - whether it is to squeeze performance in the conventionally used spectrum, already wrung dry, or signal generation and system design in the relatively emptier mm-Wave to sub-mmWave spectrum, much of the latter falling in the ``Terahertz Gap". Indeed, transistor scaling and innovative device physics leading to new transistor topologies have yielded higher cut-off frequencies in CMOS, though still lagging well behind SiGe and III-V semiconductors. To avoid multimodule solutions with functionality partitioned across different technologies, CMOS must be pushed out of its comfort zone, and technology scaling has to have accompanying breakthroughs in design approaches not only at the system but also at the block level. In this thesis, while not targeting a specific application, we seek to formulate the obstacles in synthesizing high frequency, high power and low noise signals in CMOS and construct a coherent design methodology to address them. Based on this, three novel prototypes to overcome the limiting factors in each case are presented. The first half of this thesis deals with high frequency signal synthesis and power generation in CMOS. Outside the range of frequencies where the transistor has gain, frequency generation necessitates harmonic extraction either as harmonic oscillators or as frequency multipliers. We augment the traditional maximum oscillation frequency metric (fmax), which only accounts for transistor losses, with passive component loss to derive an effective fmax metric. We then present a methodology for building oscillators at this fmax, the Maximum Gain Ring Oscillator. Next, we explore generating large signals beyond fmax through harmonic extraction in multipliers. Applying concepts of waveform shaping, we demonstrate a Power Mixer that engineers transistor nonlinearity by manipulating the amplitudes and relative phase shifts of different device nodes to maximize performance at a specific harmonic beyond device cut-off. The second half proposes a new architecture for an ultra-low noise phase-locked loop (PLL), the Reference-Sampling PLL. In conventional PLLs, a noisy buffer converts the slow, low-noise sine-wave reference signal to a jittery square-wave clock against which the phase of a noisy voltage-controlled oscillator (VCO) is corrected. We eliminate this reference buffer, and measure phase error by sampling the reference sine-wave with the 50x faster VCO waveform already available on chip, and selecting the relevant sample with voltage proportional to phase error. By avoiding the N-squared multiplication of the high-power reference buffer noise, and directly using voltage-mode phase error to control the VCO, we eliminate several noisy components in the controlling loop for ultra-low integrated jitter for a given power consumption. Further, isolation of the VCO tank from any varying load, unlike other contemporary divider-less PLL architectures, results in an architecture with record performance in the low-noise and low-spur space. We conclude with work that brings together concepts developed for clean, high-power signal generation towards a hybrid CMOS-Optical approach to Frequency-Modulated Continuous-Wave (FMCW) Light-Detection-And-Ranging (LIDAR). Cost-effective tunable lasers are temperature-sensitive and have nonlinear tuning profiles, rendering precise frequency modulations or 'chirps' untenable. Locking them to an electronic reference through an electro-optic PLL, and electronically calibrating the control signal for nonlinearity and ambient sensitivity, can make such chirps possible. Approaches that build on the body of advances in electrical PLLs to control the performance, and ease the specification on the design of optical systems are proposed. Eventually, we seek to leverage the twin advantages of silicon-intensive integration and low-cost high-yield towards developing a single-chip solution that uses on-chip signal processing and phased arrays to generate precise and robust chirps for an electronically-steerable fine LIDAR beam

Frequency Multipliers in SiGe BiCMOS for Local Oscillator Generation in D-band Wireless Transceivers

Communications at millimeter-wave (mm-Wave) have drawn a lot of attention in recent years due to the wide available bandwidth which translates directly to higher data transmission capacity. Generation of the transceivers local oscillation (LO) is critical because many contrasting requirements, i.e. tuning range (TR), phase noise (PN), output power, and level of spurious tones, affect the system performance. Differently from what is commonly pursued at Radio Frequency, LO generation with a PLL embedding a VCO at the desired output frequency is not viable at mm-wave. A more promising approach consists of a PLL in the 10-20GHz range, where silicon VCOs feature the best figure of merit, followed by a frequency multiplier. In this thesis, a frequency multiplication chain is investigated to up-convert an LO signal from X-band to D-band by a multiplication factor of 12. The multiplication is done in steps of 3, 2, and 2. A sextupler chip comprises the tripler and the first doubler and the last doubler stage which upconverts the LO signal from E- to D-band is realized in a separate chip, all in a 55nm SiGe BiCMOS technology. The frequency tripler circuit is based on a novel circuit topology which yields a remarkable improvement on the suppression of the driving signal frequency at the output, compared to conventional designs exploiting transistors in class-C. The active core of the circuit approximates the transfer characteristic of a third-order polynomial that ideally produces only a third-harmonic of the input signal. Implemented in a separate break-out chip and consuming 23mW of DC power, the tripler demonstrates ~40dB suppression of the input signal and its 5th harmonic over 16% fractional bandwidth and robustness to power variation of the driving signal over a 15dB range. Including the E-band doubler, the sextupler chip achieves a peak output power of 1.7dBm at 74.4GHz and remains within 2dB variation from 70GHz to 82GHz, corresponding to 16% fractional BW. In this frequency range, the leakages of all harmonics are suppressed by more than 40dBc. The design of the D-band doubler was aimed at delivering high output power with high efficiency and high conversion gain. Toward this end, the efficiency of a push-push pair was improved by a stacked Colpitts oscillator to boost the power conversion gain by 10dB. Moreover, the common-collector configuration keeps separate the oscillator tank from the load, allowing independent optimization of the harmonic conversion efficiency and the load impedance for maximum power delivery. The measured performance of the test chip demonstrated Pout up to 8dBm at 130GHz with 13dB conversion gain and 6.3% Power Added Efficiency

A study of radio frequency converters and mixers

This thesis will present a detailed discussion of the principles of frequency conversion and the problems attendant to the design of converter stages. The topic of harmonic conversion has been singled out for a more extended treatment than is now available in the literature. This topic is the subject of the experimental investigation portion of this thesis. Harmonic conversion has applications in U-H-F receivers as well as in Double Superheterodyne Receivers . The discussion given to the frequency converter in the first section of this thesis will be without regard to any applications. General theory will be stressed, and most of the difficulties involved in successful converter circuit design will be discussed in some detail. A detailed analytical study of possible harmonic conversion circuits is included in the second major section of this thesis. Some of the analytical developments of this section are subsequently verified by experimental study. The third topical division is the presentation of the results of the experimental study on various harmonic conversion circuits, including a new circuit developed by the author --Introduction, page 5

Injection Locked Oscillator for Radiometer

The main goal of this project was to design an injection locked oscillator (ILO) with free-running frequency of 70 GHz, and with locking capability to the third and the fifth harmonics of the reference signal upon injection. The circuit was realized using the silicon-germanium (SiGe) bipolar-complementary metal-oxide-semiconductor (BiCMOS) technology and the locking condition were verified after simulating the resistor-capacitor (RC) extracted netlist of the layout. The cadence virtuoso toolkit was used for the design process and the simulation purpose. The locking phenomenon, quasi-lock and fast-beat mode, lock range upon different injection power and phase noise characteristics of the ILO upon subharmonic injection were studied. The ILO was implemented using the direct (parallel) injection topology. The designed ILO circuit consists of two main components; conventional cross-coupled oscillator with oscillation frequency of 71 GHz and harmonic generator that injects the harmonics of the reference signal into the oscillator. The nonlinearity of the transistor was studied under different biasing conditions and the optimal bias point of 0.83 V was chosen that provided the maximum frequency conversion gain. The power consumed by the core oscillator is 2.64 mW and 3.4 mW by the harmonic generator under the supply voltage of 1.2 V, making the total power consumption of 6.04 mW as a whole by the ILO. The ILO achieved the locking range (LR) of 7.9% for the fifth harmonics injection and 1.22% for the third harmonics injection of the reference signal with input injection power of 0 dBm. The oscillator even achieved 0.32% LR for the seventh harmonics injection with the injection power of 0 dBm. The corresponding frequency ranges are 18.9-24.5 GHz, 13.29-14.16 GHz, 9.8-10.03 GHz for the third, fifth and the seventh harmonics respectively