Computers Without Clocks

Continuing increases in logic' density on VLSI chips have led to increasing problems with clock distribution systems. This has stimulated interest in dispensing with the clock s that contra I virtually all existing digital systems. The recent construction at Cal tech of a microprocessor chip without a clock has clearly demonstrated the feasibility of such systems. Basic principles that can be used to design computers without clocks are outlined here. Handshaking and dual-rail coding constitute one important related pair of concepts. Logic circuit level designs of asynchronous registers. counters. shift registers. and adders are shown. Control modules are described that can be used as building blocks for systems of varying complexity. These can he used to implement all of the basic features of modern computers including interrupts and pipelines. The design of an asynchronous add-and-shift binary multiplier is used to illustrate the use of these data processing and control modules. Most of the work shown uses what is generally referred to as 4-phase handshaking. but 2-phase handshaking is also discussed. The extent to which unclocked systems can be truIy delay - insensitive is discussed

A Necessary and Sufficient Timing Assumption for Speed-Independent Circuits

This paper presents a proof that the adversary path timing assumption is both necessary and sufficient for correct SI circuit operation. This assumption requires that the delay of a wire on one branch of a fork be less than the delay through a gate sequence beginning at another branch in the same fork. Both the definition of the timing assumption and the proof build on a general, formal notion of computation given with respect to production rule sets. This underlying framework can be used for a variety of proof efforts or as a basis for defining other useful notions involving asynchronous computation

Covering conditions and algorithms for the synthesis of speed-independent circuits

Journal ArticleAbstract-This paper presents theory and algorithms for the synthesis of standard C-implementations of speed-independent circuits. These implementations are block-level circuits which may consist of atomic gates to perform complex functions in order to ensure hazard freedom. First, we present Boolean covering conditions that guarantee that the standard C-implementations operate correctly. Then, we present two algorithms that produce optimal solutions to the covering problem. The first algorithm is always applicable, but does not complete on large circuits. The second algorithm, motivated by our observation that our covering problem can often be solved with a single cube, finds the optimal single-cube solution when such a solution exists. When applicable, the second algorithm is dramatically more efficient than the first, more general algorithm. We present results for benchmark specifications which indicate that our single-cube algorithm is applicable on most benchmark circuits and reduces run times by over an order of magnitude. The block-level circuits generated by our algorithms are a good starting point for tools that perform technology mapping to obtain gate-level speed independent circuits