An efficient unused integrated circuits detection algorithm for parallel scan architecture

In recent days, many integrated circuits (ICs) are operated parallelly to increase switching operations in on-chip static random access memory (SRAM) array, due to more complex tasks and parallel operations being executed in many digital systems. Hence, it is important to efficiently identify the long-duration unused ICs in the on-chip SRAM memory array layout and to effectively distribute the task to unused ICs in SRAM memory array. In the present globalization, semiconductor supply chain detection of unused SRAM in large memory arrays is a very difficult task. This also results in reduced lifetime and more power dissipation. To overcome the above-mentioned drawbacks, an efficient unused integrated circuits detection algorithm (ICDA) for parallel scan architecture is proposed to differentiate the ‘0’ and ‘1’ in a larger SRAM memory array. The proposed architecture avoids the unbalancing of ‘0’ and ‘1’ concentrations in the on-chip SRAM memory array and also optimizes the area required for the memory array. As per simulation results, the proposed method is more efficient in terms of reliability, the detection rate in both used and unused ICs and reduction of power dissipation in comparison to conventional methods such as backscattering side-channel analysis (BSCA) and network attached storage (NAS) algorithm

Quantifiable Assurance: From IPs to Platforms

Hardware vulnerabilities are generally considered more difficult to fix than software ones because they are persistent after fabrication. Thus, it is crucial to assess the security and fix the vulnerabilities at earlier design phases, such as Register Transfer Level (RTL) and gate level. The focus of the existing security assessment techniques is mainly twofold. First, they check the security of Intellectual Property (IP) blocks separately. Second, they aim to assess the security against individual threats considering the threats are orthogonal. We argue that IP-level security assessment is not sufficient. Eventually, the IPs are placed in a platform, such as a system-on-chip (SoC), where each IP is surrounded by other IPs connected through glue logic and shared/private buses. Hence, we must develop a methodology to assess the platform-level security by considering both the IP-level security and the impact of the additional parameters introduced during platform integration. Another important factor to consider is that the threats are not always orthogonal. Improving security against one threat may affect the security against other threats. Hence, to build a secure platform, we must first answer the following questions: What additional parameters are introduced during the platform integration? How do we define and characterize the impact of these parameters on security? How do the mitigation techniques of one threat impact others? This paper aims to answer these important questions and proposes techniques for quantifiable assurance by quantitatively estimating and measuring the security of a platform at the pre-silicon stages. We also touch upon the term security optimization and present the challenges for future research directions

A Non-invasive Technique to Detect Authentic/Counterfeit SRAM Chips

Many commercially available memory chips are fabricated worldwide in untrusted facilities. Therefore, a counterfeit memory chip can easily enter into the supply chain in different formats. Deploying these counterfeit memory chips into an electronic system can severely affect security and reliability domains because of their sub-standard quality, poor performance, and shorter lifespan. Therefore, a proper solution is required to identify counterfeit memory chips before deploying them in mission-, safety-, and security-critical systems. However, a single solution to prevent counterfeiting is challenging due to the diversity of counterfeit types, sources, and refinement techniques. Besides, the chips can pass initial testing and still fail while being used in the system. Furthermore, existing solutions focus on detecting a single counterfeit type (e.g., detecting recycled memory chips). This work proposes a framework that detects major counterfeit static random-access memory (SRAM) types by attesting/identifying the origin of the manufacturer. The proposed technique generates a single signature for a manufacturer and does not require any exhaustive registration/authentication process. We validate our proposed technique using 345 SRAM chips produced by major manufacturers. The silicon results show that the test scores ($F_{1}$ score) of our proposed technique of identifying memory manufacturer and part-number are 93% and 71%, respectively.Comment: This manuscript has been submitted for possible publication. Copyright may be transferred without notice, after which this version may no longer be accessibl

ASSESSMENT OF SUCCESS INDICATORS ASSOCIATED WITH MANUFACTURING IC CHIPS IN INDIAN SEMICONDUCTOR MANUFACTURING INDUSTRY

Integrated circuit plays a crucial role in reducing the size, increasing the processing speed, and enhancing the dependability on the electronic devices. Notably, the widespread use of these technologies has led to advancements in various sectors, including the communications, healthcare, and automobile industry. This study rank and identifies the critical success indicators associated with the manufacturing IC chips in the Indian semiconductor industry by employing one sample t-test approach. Based on the existing literature, the study investigates sixteen success indicators associated with the manufacturing IC chips in India. In addition, experts from the semiconductor manufacturing organization have validated these factors concerning the Indian semiconductor industry. The research concludes that “Monitor the Time-to-Market (SI7)”, “Enhance Customer Satisfaction (SI13)”, “Assess the Yield Rate (SI11)”, and “Calculate the Return on Investment (ROI) for Cost (SI5)”, are the critical success indicators associated with manufacturing of IC chips, as per the t-test analysis from 152 respondents working in the semiconductor sectors. The findings have multiple implications for businesses and policymaker, and can assist various stakeholders, including global semiconductor companies, domestic manufacturers, and fabless semiconductor firm

Design, Fabrication, and Run-time Strategies for Hardware-Assisted Security

Today, electronic computing devices are critically involved in our daily lives, basic infrastructure, and national defense systems. With the growing number of threats against them, hardware-based security features offer the best chance for building secure and trustworthy cyber systems. In this dissertation, we investigate ways of making hardware-based security into a reality with primary focus on two areas: Hardware Trojan Detection and Physically Unclonable Functions (PUFs). Hardware Trojans are malicious modifications made to original IC designs or layouts that can jeopardize the integrity of hardware and software platforms. Since most modern systems critically depend on ICs, detection of hardware Trojans has garnered significant interest in academia, industry, as well as governmental agencies. The majority of existing detection schemes focus on test-time because of the limited hardware resources available at run-time. In this dissertation, we explore innovative run-time solutions that utilize on-chip thermal sensor measurements and fundamental estimation/detection theory to expose changes in IC power/thermal profile caused by Trojan activation. The proposed solutions are low overhead and also generalizable to many other sensing modalities and problem instances. Simulation results using state-of-the-art tools on publicly available Trojan benchmarks verify that our approaches can detect Trojans quickly and with few false positives. Physically Unclonable Functions (PUFs) are circuits that rely on IC fabrication variations to generate unique signatures for various security applications such as IC authentication, anti-counterfeiting, cryptographic key generation, and tamper resistance. While the existence of variations has been well exploited in PUF design, knowledge of exactly how variations come into existence has largely been ignored. Yet, for several decades the Design-for-Manufacturability (DFM) community has actually investigated the fundamental sources of these variations. Furthermore, since manufacturing variations are often harmful to IC yield, the existing DFM tools have been geared towards suppressing them (counter-intuitive for PUFs). In this dissertation, we make several improvements over current state-of-the-art work in PUFs. First, our approaches exploit existing DFM models to improve PUFs at physical layout and mask generation levels. Second, our proposed algorithms reverse the role of standard DFM tools and extend them towards improving PUF quality without harming non-PUF portions of the IC. Finally, since our approaches occur after design and before fabrication, they are applicable to all types of PUFs and have little overhead in terms of area, power, etc. The innovative and unconventional techniques presented in this dissertation should act as important building blocks for future work in cyber security

Internet of Things Strategic Research Roadmap

Internet of Things (IoT) is an integrated part of Future Internet including existing and evolving Internet and network developments and could be conceptually defined as a dynamic global network infrastructure with self configuring capabilities based on standard and interoperable communication protocols where physical and virtual “things” have identities, physical attributes, and virtual personalities, use intelligent interfaces, and are seamlessly integrated into the information network