Design of a Fully Autonomous Mobile Pipeline Exploration Robot (FAMPER)

Pipelines have been an integral part of our constructions for many centuries. However, need to be maintained, and the cost of maintenance continues to increase. Robots have been considered as an attractive alternative, and many different types of pipeline robots have been proposed in the past. Unfortunately many of them work under only very restricted environments such as customized pipelines, often have no vertical mobility, or can traverse through only a simple pipeline structure due to wired control. This thesis presents the design and implementation of a robot based on novel idea we call “caterpillar navigational mechanism”. A Fully Autonomous Mobile Pipeline Exploration Robot (FAMPER), for exploring pipeline structures autonomously has been built and its performance has been evaluated. We present the design of a robot based on wall-pressed caterpillar type for not only horizontal, but also vertical mobility in pipeline elements such as straight pipelines, elbows and branches, and its autonomous navigational system providing useful information for pipeline maintenance. FAMPER has been designed for 6 inch sewer pipes, which are predominantly used in urban constructions. The proposed design enables FAMPER to display formidable mobility and controllability in most of the existing structure of pipeline, and provides a spacious body for housing various electronic devices. Specifically, FAMPER is equipped with several sensors, and a high performance processor for autonomous navigation. We have performed experiments to evaluate the effectiveness of our architecture and we present here a discussion of the performed results

Empowering parallel computing with field programmable gate arrays

After more than 30 years, reconfigurable computing has grown from a concept to a mature field of science and technology. The cornerstone of this evolution is the field programmable gate array, a building block enabling the configuration of a custom hardware architecture. The departure from static von Neumannlike architectures opens the way to eliminate the instruction overhead and to optimize the execution speed and power consumption. FPGAs now live in a growing ecosystem of development tools, enabling software programmers to map algorithms directly onto hardware. Applications abound in many directions, including data centers, IoT, AI, image processing and space exploration. The increasing success of FPGAs is largely due to an improved toolchain with solid high-level synthesis support as well as a better integration with processor and memory systems. On the other hand, long compile times and complex design exploration remain areas for improvement. In this paper we address the evolution of FPGAs towards advanced multi-functional accelerators, discuss different programming models and their HLS language implementations, as well as high-performance tuning of FPGAs integrated into a heterogeneous platform. We pinpoint fallacies and pitfalls, and identify opportunities for language enhancements and architectural refinements

Arctic Standards: Recommendations on Oil Spill Prevention, Response, and Safety in the U.S. Arctic Ocean

Oil spilled in Arctic waters would be particularly difficult to remove. Current technology has not been proved to effectively clean up oil when mixed with ice or when trapped under ice. An oil spill would have a profoundly adverse impact on the rich and complex ecosystem found nowhere else in the United States. The Arctic Ocean is home to bowhead, beluga, and gray whales; walruses; polar bears; and other magnificent marine mammals, as well as millions of migratory birds. A healthy ocean is important for these species and integral to the continuation of hunting and fishing traditions practiced by Alaska Native communities for thousands of years.To aid the United States in its efforts to modernize Arctic technology and equipment standards, this report examines the fierce Arctic conditions in which offshore oil and gas operations could take place and then offers a summary of key recommendations for the Interior Department to consider as it develops world-class, Arctic-specific regulatory standards for these activities. Pew's recommendations call for improved technology,equipment, and procedural requirements that match the challenging conditions in the Arctic and for full public participation and transparency throughout the decision-making process. Pew is not opposed to offshore drilling, but a balance must be achieved between responsible energy development and protection of the environment.It is essential that appropriate standards be in place for safety and for oil spill prevention and response in this extreme, remote, and vulnerable ecosystem. This report recommends updating regulations to include Arctic specific requirements and codifying temporary guidance into regulation. The appendixes to this report provide substantially more detail on the report's recommendations, including technical background documentation and additional referenced materials. Please refer to the full set of appendixes for a complete set of recommendations. This report and its appendixes offer guidelines for responsible hydrocarbon development in the U.S. Arctic Ocean

High-level synthesis optimization for blocked floating-point matrix multiplication

In the last decade floating-point matrix multiplication on FPGAs has been studied extensively and efficient architectures as well as detailed performance models have been developed. By design these IP cores take a fixed footprint which not necessarily optimizes the use of all available resources. Moreover, the low-level architectures are not easily amenable to a parameterized synthesis. In this paper high-level synthesis is used to fine-tune the configuration parameters in order to achieve the highest performance with maximal resource utilization. An\ exploration strategy is presented to optimize the use of critical resources (DSPs, memory) for any given FPGA. To account for the limited memory size on the FPGA, a block-oriented matrix multiplication is organized such that the block summation is done on the CPU while the block multiplication occurs on the logic fabric simultaneously. The communication overhead between the CPU and the FPGA is minimized by streaming the blocks in a Gray code ordering scheme which maximizes the data reuse for consecutive block matrix product calculations. Using high-level synthesis optimization, the programmable logic operates at 93% of the theoretical peak performance and the combined CPU-FPGA design achieves 76% of the available hardware processing speed for the floating-point multiplication of 2K by 2K matrices

A Fast and Accurate Cost Model for FPGA Design Space Exploration in HPC Applications

Heterogeneous High-Performance Computing (HPC) platforms present a significant programming challenge, especially because the key users of HPC resources are scientists, not parallel programmers. We contend that compiler technology has to evolve to automatically create the best program variant by transforming a given original program. We have developed a novel methodology based on type transformations for generating correct-by-construction design variants, and an associated light-weight cost model for evaluating these variants for implementation on FPGAs. In this paper we present a key enabler of our approach, the cost model. We discuss how we are able to quickly derive accurate estimates of performance and resource-utilization from the design’s representation in our intermediate language. We show results confirming the accuracy of our cost model by testing it on three different scientific kernels. We conclude with a case-study that compares a solution generated by our framework with one from a conventional high-level synthesis tool, showing better performance and power-efficiency using our cost model based approach