FPU designs with NEM relays

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.This electronic version was submitted by the student author. The certified thesis is available in the Institute Archives and Special Collections.Includes bibliographical references (pages 71-74).Nano-electromechanical (NEM) relays are an alternative to CMOS transistors as the fabric of digital circuits. Circuits with NEM relays offer energy-efficiency benefits over CMOS since they have zero leakage power and are strategically designed to maintain throughput that is competitive with CMOS despite their slow actuation times. The floating-point unit (FPU) is the most complex arithmetic unit in a computational system. This thesis investigates if the energy-efficiency promise of NEM relays demonstrated before on smaller circuit blocks holds for complex computational structures such as the FPU. The energy, performance, and area trade-offs of FPU designs with NEM relays are examined and compared with that of state-of-the-art CMOS designs in an equivalent scaled process. Circuits that are critical path bottlenecks, including primarily the leading zero detector (LZD) and leading zero anticipator (LZA) blocks, are carefully identified and optimized for low latency and device count. We manage to drop the NEM relay FPU latency from 71 mechanical delays in a CMOS-style implementation to 16 mechanical delays in a NEM relay pass-logic style implementation. The FPU designed with NEM relays features 15x lower energy per operation compared to CMOS.by Sumit Dutta.S.M

Design and demonstration of integrated micro-electro-mechanical relay circuits for VLSI applications

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.Includes bibliographical references (p. 115-121).Complementary-Metal-Oxide-Semiconductor (CMOS) feature size scaling has resulted in significant improvements in the performance and energy efficiency of integrated circuits in the past 4 decades. However, in the last decade and for technology nodes below 90 nm, the scaling of threshold and supply voltages has slowed, as a result of subthreshold leakage, and power density has increased with each new technology node. This has forced a move toward multi-core architectures, but the energy efficiency benefits of parallelism are limited by the sub-thresahold leakage and the minimum energy point for a given function. Avoiding this roadblock requires an alternative device with more ideal switching characteristics. One promising class of such devices is the electro-statically actuated micro-electro-mechanical (MEM) relay which offers zero leakage current and abrupt turn-on behavior. Although a MEM relay is inherently slower than a CMOS transistor due to the mechanical movement, we have developed circuit design methodologies to mitigate this problem at the system level. This thesis explores such design optimization techniques and investigates the viability of MEM relays as an alternative switching technology for very-large scale integration (VLSI) applications. In the first part of this thesis, the feasibility of MEM relays for power management applications is discussed. Due to their negligibly low leakage, in certain applications, chips utilizing power gates built with MEM relays can achieve lower total energy than those built with CMOS transistors. A simple comparative analysis is presented and provides design guidelines and energy savings estimates as a function of technology parameters, and quantifies the further benefits of scaled relay designs. We also demonstrate a relay chip successfully power-gating a CMOS chip, and show a relay-based pulse generator suitable for self-timed operation. Going beyond power-gating applications, this work also describes circuit techniques and trade-offs for logic design with MEM-relays, focusing on multipliers which are commonly known as the most complex arithmetic units in a digital system. These techniques leverage the large disparity between mechanical and electrical time-constants of a relay, partitioning the logic into large, complex gates to minimize the effect of mechanical delay and improve circuit performance. At the component design level, innovations in compressor unit design minimize the required number of relays for each block and facilitate component cascading with no delay penalty. We analyze the area/energy/delay trade-offs vs. CMOS designs, for typical bit-widths, and show that scaled relays offer 10-20x lower energy per operation for moderate throughputs (<10-100MOPS). In addition to this analysis, we demonstrate the functionality of some of the most complex MEM relay circuits reported to date. Finally, considering the importance of signal generation and transmission in VLSI systems, this thesis presents MEM relay-based I/O units, focusing on design and demonstration of digital to analog converters (DAC). It also explores the concept of faster-than-mechanical-delay signal transmission.by Hossein Fariborzi.Ph.D

DEVELOPMENT OF NANO/MICROELECTROMECHANICAL SYSTEM (N/MEMS) SWITCHES

Ph.DDOCTOR OF PHILOSOPH

Energy-efficient wireless sensors : fewer bits, Moore MEMS

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2011.Cataloged from PDF version of thesis. Page 184 blank.Includes bibliographical references (p. 171-183).Adoption of wireless sensor network (WSN) technology could enable improved efficiency across a variety of industries that include building management, agriculture, transportation, and health care. Most of the technical challenges of WSNs can be linked to the stringent energy constraints of each sensor node, where wireless communication and leakage energy are the doninant components of active and idle energy costs. To address these two limitations, this thesis adopts compressed sensing (CS) theory as a generic source coding framework to minimize the transmitted data and proposes the use of micro-electro-mechanical (MEM) relay technology to eliminate the idle leakage. To assess the practicality of adopting CS as a source coding framework we examine the inpact of finite resources, input noise, and wireless channel impairments on the compression and reconstruction performance of CS. We show that CS, despite being a lossy compression algorithm, can realize compression factors greater than loX with no loss in fidelity for sparse signals quantized to medium resolutions. We also model the hardware costs for implementing the CS encoder and results from a test chip designed in a 90 nm CMOS process that consumes only 1.9 [mu]W for operating frequencies below 20 kHz, verifies the models. The encoder is desioned to enable continuous, on-the-fly compression that is demonstrated on electroencephalography (EEG) and electrocardiogram (EKG) signals to show the applicability of CS. To address sub-threshold leakage, which limits the energy performance in CMOS-based sensor nodes, we develop design methodologies towards leveraging the zero leakage characteristics of MEM relays while overcoming their slower switching speeds. Projections on scaled relay circuits show the potential for greater than loX improvements in energy efficieicy over CMOS at up to 10-100 Mops for a variety of circuit sub-systems. Experimental results demonstrating functionality for several circuit building blocks validate the viability of the technology, while feedback from these results is used to refine the device design. Incorporating all of the design elements, w present simnulation results for our most recent test chip design which implements relay-based versions of the CS encoder circuits in a 0.25 jim lithographic process showing 5X improvement over our 90 nm CMOS design.by Fred Chen.Ph.D