Design of bias circuit for charge pump in 130nm BiCMOS technology

El presente trabajo muestra el diseño de un circuito de polarización en la tecnología de 130nm BiCMOS con las herramientas de diseño de Cadence. El circuito de polarización es parte de un circuito Charge Pump (CP), el cual a su vez es parte de un circuito PLL (Phased Locked Loop) que se utilizará en una implementación de señal mixta de un Recuperador de Datos (CDR). Al inicio del trabajo se presenta una descripción general de los módulos analógicos y digitales que conforman el proyecto. La topología de diseño propuesta refleja la enorme dependencia del circuito de polarización con el circuito CP. Un circuito replica permite “seguir” las variaciones de carga y descarga de corriente del circuito CP para compensar mediante un OTA (Operational Transconductance Amplifier) el nivel de voltaje requerido en los transistores del circuito diferencial del CP. El proceso de diseño, la generación de esquemáticos y bancos de pruebas son mostrados durante los primeros capítulos del trabajo. La verificación del diseño pre-layout a través del proceso de esquinas, así como el uso el uso de las herramientas de verificación de reglas de diseño post-layout son mostradas durante los capítulos finales.The present work shows the design of a Bias circuit in 130 nm of BiCMOS process using Cadence tools. The Bias circuit is part of a Charge Pump (CP) circuit, which in turn is one block of a PLL (Phased Locked Loop) that will be used in a mixed-signal implementation of a Clock and Data Recovery (CDR) circuit. This PLL-based CDR is the project of the generation 2018 of the Specialty in System on a Chip at ITESO. A general description of the analog and digital modules that make up this project is shown at the beginning of this work. As it is described in detail in this work, the proposed design topology reveals the enormous dependence of the polarization circuit to the CP circuit. The replica method used in the Bias circuit allows to "follow" the current variations of CP charge/discharge process to compensate through an OTA (Operational Transconductance Amplifier) the level of voltage required by the tail transistors of CP circuit. The design procedure, the generation of schematics and test benches are shown during the first chapters of this work. The verification of the pre-layout design through the corners process, as well as the use of the post-layout design rules verification tools, are shown during the final chapters of this work.Consejo Nacional de Ciencia y Tecnologí

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A Phase-locked loop (PLL) is a basic control system that attempts to produce an output waveform that can match with the input reference signal in the shortest time possible. A filter is one of the main components in the PLL blocks, and it plays a very important role to determine the range of input frequency that can ensure the system stays in a locked condition. This paper focuses on designing a fixed-pole active PI filter which is suitable for high-frequency PLL-based circuits such as those used in clock generators. As PLL is bound to fall out of lock due to the nonlinear effects from its phase detector, a new approach is introduced in this work which is to combine the linear and nonlinear control method to ensure stability. Having had the phase margin specified a priori, it is shown by simulation that the allowable range of input frequency such that the system remains locked can be expanded

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