Millimeter-Scale and Energy-Efficient RF Wireless System

This dissertation focuses on energy-efficient RF wireless system with millimeter-scale dimension, expanding the potential use cases of millimeter-scale computing devices. It is challenging to develop RF wireless system in such constrained space. First, millimeter-sized antennae are electrically-small, resulting in low antenna efficiency. Second, their energy source is very limited due to the small battery and/or energy harvester. Third, it is required to eliminate most or all off-chip devices to further reduce system dimension. In this dissertation, these challenges are explored and analyzed, and new methods are proposed to solve them. Three prototype RF systems were implemented for demonstration and verification. The first prototype is a 10 cubic-mm inductive-coupled radio system that can be implanted through a syringe, aimed at healthcare applications with constrained space. The second prototype is a 3x3x3 mm far-field 915MHz radio system with 20-meter NLOS range in indoor environment. The third prototype is a low-power BLE transmitter using 3.5x3.5 mm planar loop antenna, enabling millimeter-scale sensors to connect with ubiquitous IoT BLE-compliant devices. The work presented in this dissertation improves use cases of millimeter-scale computers by presenting new methods for improving energy efficiency of wireless radio system with extremely small dimensions. The impact is significant in the age of IoT when everything will be connected in daily life.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/147686/1/yaoshi_1.pd

Courseware and curriculum development for a wireless electronics class

Thesis (M. Eng.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2007.Includes bibliographical references (p. 169-170).The design of basic wireless building blocks (such as oscillators, amplifiers, and modulation circuits) and modern encoding techniques such as CDMA (Code Division Multiple Access) are in high demand by employers of recent graduates. This thesis sets forth a lesson plan and laboratory kit design to be used in the development of a new class that teaches these wireless system design techniques. Such a class will help students gain both the theoretical and practical experience required of them in today's industry.by Ariel Rodriguez.M.Eng

Analysis and Design of Energy Efficient Frequency Synthesizers for Wireless Integrated Systems

Advances in ultra-low power (ULP) circuit technologies are expanding the IoT applications in our daily life. However, wireless connectivity, small form factor and long lifetime are still the key constraints for many envisioned wearable, implantable and maintenance-free monitoring systems to be practically deployed at a large scale. The frequency synthesizer is one of the most power hungry and complicated blocks that not only constraints RF performance but also offers subtle scalability with power as well. Furthermore, the only indispensable off-chip component, the crystal oscillator, is also associated with the frequency synthesizer as a reference. This thesis addresses the above issues by analyzing how phase noise of the LO affect the frequency modulated wireless system in different aspects and how different noise sources in the PLL affect the performance. Several chip prototypes have been demonstrated including: 1) An ULP FSK transmitter with SAR assisted FLL; 2) A ring oscillator based all-digital BLE transmitter utilizing a quarter RF frequency LO and 4X frequency multiplier; and 3) An XO-less BLE transmitter with an RF reference recovery receiver. The first 2 designs deal with noise sources in the PLL loop for ultimate power and cost reduction, while the third design deals with the reference noise outside the PLL and explores a way to replace the XO in ULP wireless edge nodes. And at last, a comprehensive PN theory is proposed as the design guideline.PHDElectrical EngineeringUniversity of Michigan, Horace H. Rackham School of Graduate Studieshttps://deepblue.lib.umich.edu/bitstream/2027.42/153420/1/chenxing_1.pd

The influence of the hysteresis comparator delay on the central frequency of an asynchronous sigma-delta modulator

U radu su opisane osnovne karakteristike sinkronog i asinkronog sigma-delta (ASD) modulatora i dan je pregled trenutnog stanja u području primjene sigma-delta (SD) modulatora. U svrhu usporedbe, opisane su osnovne razlike izmeñu sinkrone i asinkrone izvedbe SD modulatora. Provedena je analiza utjecaja vremena kašnjenja komparatora s histerezom na radne značajke ASD modulatora. Matematičkim proračunima, računalnom simulacijom i izvedenim mjerenjima na modelima pokazano je smanjenje središnje frekvencije zbog utjecaja vremena kašnjenja. Za smanjenje nepoželjnog utjecaja vremena kašnjenja na radne značajke ASD modulatora predložene su dvije metode. Prva metoda se zasniva na ograničenju izlaznog signala iz integratora, čime se ostvaruje povećanje izlazne frekvencije (metoda 1), dok se kod druge metode uvodi amplitudna modulacija napona pragova histereze koja izlazni signal integratora postavlja unutar vrijednosti proračunatih napona pragova histereze. Na temelju matematičkog modela ASD modulatora, za potrebe simulacije utjecaja vremena kašnjenja i metoda za poboljšanje (metoda 1 i metoda 2), kreiran je Simulink model u programskom alatu Matlab®. U Matlab okruženju simuliran je i sklop za pretvorbu 1- bitovnog ASD signala govornog pojasa (frekvencija do 4 kHz) u sinkroni PCM m-bitovni digitalni signal. U simulacijskom programu Multisim Analog Devices Edition simulacijski model ASD modulatora primijenjen je na pojačalo snage D klase na kojem je takoñer ispitana metoda 2. Za verifikaciju matematičkih modela mjerenjima izrañen je laboratorijski model ASD modulatora s mogućnošću primjene metode 1 i 2. Rezultatima mjerenja na laboratorijskom modelu ASD modulatora potvrñeno je poboljšanje radnih značajki ASD modulatora primjenom navedenih metoda. Na sklopu pojačala snage D klase izmjereno je ukupno harmonijsko izobličenje izlaznog signala. Dokazano je da se primjenom metode 2 faktor ukupnog harmonijskog izobličenja smanjuje u cijelom rasponu amplituda ulaznog signala.The basics properties of the synchronous and asynchronous sigma-delta (ASD) modulators have been described and current state-of-art in sigma-delta modulation applications has been reported. For comparison, the major differences between synchronous and asynchronous SD modulators have been described. Analysis of hysteresis comparator propagation delay influence to the ASD modulator performances has been provided. The mathematical analysis, computer simulations and measurement results confirm the central frequency detoriation due to propagation delay influence. For propagation delay compensation two methods have been proposed. The first method is based on limitation of the integrator output voltage (method 1), which increses ASD central frequency, while second method introduce hysteresis threshold voltage amplitude modulation which keeps the integrator output voltage within calculated hysteresis threshold levels. Based on the mathematical model of the ASD modulator, for simulation purposes of the propagation delay influence and the proposed method for propagation delay compensation (method 1 and method 2), Simulink model in Matlab® has been created. Matlab implementation of the A/D converter circuit for 1-bit ASD signal to synchronous PCM m-bit digital word for voice-band applications has also been proposed. Using Multisim Analog Devices Edition, simulation model of ASD modulator has been applied to class-D power amplifier for method 2 verification. For measurement results, the ASD modulator ciruit has been implemented with possibility for method 1 and method 2 application. The measuerment results on the ASD circuit confirm the mathematical analysis for the propagation delay influence and compensation method contributions which improve ASD modulator performances. For ASD modulator application in class-D power amplifier, total harmonic distorsion has been measured. It has been shown that method 2 implementation reduces total harmonic distorsion of output signal for full range of input signal amplitudes

NEGATIVE BIAS TEMPERATURE INSTABILITY STUDIES FOR ANALOG SOC CIRCUITS

Negative Bias Temperature Instability (NBTI) is one of the recent reliability issues in sub threshold CMOS circuits. NBTI effect on analog circuits, which require matched device pairs and mismatches, will cause circuit failure. This work is to assess the NBTI effect considering the voltage and the temperature variations. It also provides a working knowledge of NBTI awareness to the circuit design community for reliable design of the SOC analog circuit. There have been numerous studies to date on the NBTI effect to analog circuits. However, other researchers did not study the implication of NBTI stress on analog circuits utilizing bandgap reference circuit. The reliability performance of all matched pair circuits, particularly the bandgap reference, is at the mercy of aging differential. Reliability simulation is mandatory to obtain realistic risk evaluation for circuit design reliability qualification. It is applicable to all circuit aging problems covering both analog and digital. Failure rate varies as a function of voltage and temperature. It is shown that PMOS is the reliabilitysusceptible device and NBTI is the most vital failure mechanism for analog circuit in sub-micrometer CMOS technology. This study provides a complete reliability simulation analysis of the on-die Thermal Sensor and the Digital Analog Converter (DAC) circuits and analyzes the effect of NBTI using reliability simulation tool. In order to check out the robustness of the NBTI-induced SOC circuit design, a bum-in experiment was conducted on the DAC circuits. The NBTI degradation observed in the reliability simulation analysis has given a clue that under a severe stress condition, a massive voltage threshold mismatch of beyond the 2mV limit was recorded. Bum-in experimental result on DAC proves the reliability sensitivity of NBTI to the DAC circuitry

Energy and area efficient techniques for data converters

Data converters are ubiquitous building blocks of a signal chain. The rapid increase in communication and connectivity devices presents new avenues for pushing the state of the art analog to digital converters. Techniques for improving resolution, bandwidth, linearity and bit-error rate, while reducing the power, energy and area is the motivation for this research. This research focuses on achieving this goal by enabling circuit techniques, architecture techniques and calibration methods. The following techniques are proposed for enabling power, area and energy efficient analog to digital converter techniques. 1. A capacitor switching scheme for successive approximation ADC is introduced to enable 93.4% energy reduction and 75 % reduction in capacitor area as compared to a conventional SAR ADCs. 2. Asynchronous correlated level shifting technique for improving current source linearity and power supply rejection ratio of zero crossing based circuits is proposed. This technique enables asynchronous ADC architectures for energy efficient system. 3. Unified gain enhancement model is proposed to catalogue gain enhancement techniques. Class-A+ and Replicated Parallel Gain Enhancement (RPGe) amplifiers are introduced as parallel gain enhancement techniques for switched capacitor circuits. A prototype pipelined ADC using RPGE amplifier achieves 74.9 dB SNDR, 90.8 dB SFDR, 87 dB THD at 20 MS/s. Built in 1P4M 0.18 μm technology and operating at 1.3 V supply, the ADC consumes 5.9 mW. The ADC occupies 3.06 sq. mm and has a figure of merit of 65 fJ /conversion step. Extracted simulation results of the prototype pipeline ADC using dynamic RPGE amplifier achieve 74 dB SNDR, 90 dB SFDR, and 85 dB THD at 30 MS /s in a 0.18 μm process. The ADC consumes 6.6 mW from a 1.3 V supply and achieves a figure of merit of 40 fJ/C-S. 4. A low-gain amplifier based V-T converter is utilized along with a TDC to replace the function of flash ADC and the DAC references in a pipeline ADC. The simulated/ extracted performance of the chip is 12bit, 100 MHz in 65nm process while consuming approximately 8-9 mA from 1 V supply. 5. A measurement technique for detecting and correcting bit-error rate in ADCs is proposed. This multi-path ADC technique squares the bit-error rate of the ADC without consuming additional analog power. The area increase is negligible compared to the conventional modular redundancy techniques. This technique can be applied to digitally detect and correct single event transients for ADCs. A three-path ADC can restore the ADC performance independent of the input frequency and number of errors in a single path. 6. LMS algorithm is used to estimate the VCO non-linearity by using the VCO as a Nyquist ADC and utilizing a slow but accurate ADC. The simulated ADC performance improves from 5 bits to 7.8 bits by using a second order fit to the VCO non-linearity