A Fully Programmable Analog Window Comparator

This paper presents a novel design of analog window comparator circuit. The comparator can adaptively adjust its error threshold according to the magnitude of input signal levels. In addition, the circuit can be digitally programmed to realize different error threshold adapting schemes. The design is fabricated using a 0.18mum CMOS technology. Testing results of the fabricated chip are also presented

Design of Window Comparators for Integrator-Based Capacitor Array Testing Circuits

This paper investigates the impact of window comparator threshold variations on the performance of integrator-based programmable capacitor array (PCA) testing circuits. It presents two window comparator designs that take different approaches to address the problem of comparator threshold variations in PCA testing. The first comparator design utilizes a fully symmetric circuit structure to achieve small threshold deviations. The second design relies on increasing testing time to reduce the effect of comparator threshold variations. Experimental results are presented to compare the performance of the two design approaches

A Programmable Window Comparator for Analog Online Testing

This paper discusses the challenge of designing window comparators for analog online testing applications. A programmable window comparator with adaptive error threshold is presented. Experimental results demonstrate that improved fault detection capability is achieved by using the proposed design. Measurement results of the fabricated comparator circuit are also presented

BATTERY ALARM MONITORING SYSTEM

Battery is used to supply the power to the load and is widely used in electrical appliances such as uninterruptable power source (UPS). UPS will supply the power during emergency or power failure. This project will explore battery monitoring system in UPS. Battery Alarm Monitoring System (BAMS) is designed to monitor the battery voltage and reduced the cost for monitoring the battery in UPS. The focus of this monitoring system is to identify the bad batteries in real time. This project is able to reduce the cost and time for preventive maintenance and avoid battery breakdown. The background of the project is discussed to get a clear view of the project. Furthermore, the problem statement of this project will be stated to address the main purpose and significance of conducting this project. The objective of this project and also the scope of study will be touched in detail. Next, the detailed of literature review will be presented. The concept and basic understanding of the project is discussed for better understanding. Moreover, the methodology, design and simulation as well as the key milestones are presented in detail. The project prototype is produced with discussion of results obtained. Lastly, the conclusion and recommendation for the project are concluded and proposed

BATTERY ALARM MONITORING SYSTEM

Battery is used to supply the power to the load and is widely used in electrical appliances such as uninterruptable power source (UPS). UPS will supply the power during emergency or power failure. This project will explore battery monitoring system in UPS. Battery Alarm Monitoring System (BAMS) is designed to monitor the battery voltage and reduced the cost for monitoring the battery in UPS. The focus of this monitoring system is to identify the bad batteries in real time. This project is able to reduce the cost and time for preventive maintenance and avoid battery breakdown. The background of the project is discussed to get a clear view of the project. Furthermore, the problem statement of this project will be stated to address the main purpose and significance of conducting this project. The objective of this project and also the scope of study will be touched in detail. Next, the detailed of literature review will be presented. The concept and basic understanding of the project is discussed for better understanding. Moreover, the methodology, design and simulation as well as the key milestones are presented in detail. The project prototype is produced with discussion of results obtained. Lastly, the conclusion and recommendation for the project are concluded and proposed

A re-configurable pipeline ADC architecture with built-in self-test techniques

High-performance analog and mixed-signal integrated circuits are integral parts of today\u27s and future networking and communication systems. The main challenge facing the semiconductor industry is the ability to economically produce these analog ICs. This translates, in part, into the need to efficiently evaluate the performance of such ICs during manufacturing (production testing) and to come up with dynamic architectures that enable the performance of these ICs to be maximized during manufacturing and later when they\u27re operating in the field. On the performance evaluation side, this dissertation deals with the concept of Built-In-Self-Test (BIST) to allow the efficient and economical evaluation of certain classes of high-performance analog circuits. On the dynamic architecture side, this dissertation deals with pipeline ADCs and the use of BIST to dynamically, during production testing or in the field, re-configure them to produce better performing ICs.;In the BIST system proposed, the analog test signal is generated on-chip by sigma-delta modulation techniques. The performance of the ADC is measured on-chip by a digital narrow-band filter. When this system is used on the wafer level, significant testing time and thus testing cost can be saved.;A re-configurable pipeline ADC architecture to improve the dynamic performance is proposed. Based on dynamic performance measurements, the best performance configuration is chosen from a collection of possible pipeline configurations. This basic algorithm can be applied to many pipeline analog systems. The proposed grouping algorithm cuts down the number of evaluation permutation from thousands to 18 for a 9-bit ADC thus allowing the method to be used in real applications.;To validate the developments of this dissertation, a 40MS/s 9-bit re-configurable pipeline ADC was designed and implemented in TSMC\u27s 0.25mum single-poly CMOS digital process. This includes a fully differential folded-cascode gain-boosting operational amplifier with high gain and high unity-gain bandwidth. The experimental results strongly support the effectiveness of reconfiguration algorithm, which provides an average of 0.5bit ENOB improvement among the set of configurations. For many applications, this is a very significant performance improvement.;The BIST and re-configurability techniques proposed are not limited to pipeline ADCs only. The BIST methodology is applicable to many analog systems and the re-configurability is applicable to any analog pipeline system

Infrastructures and Algorithms for Testable and Dependable Systems-on-a-Chip

Every new node of semiconductor technologies provides further miniaturization and higher performances, increasing the number of advanced functions that electronic products can offer. Silicon area is now so cheap that industries can integrate in a single chip usually referred to as System-on-Chip (SoC), all the components and functions that historically were placed on a hardware board. Although adding such advanced functionality can benefit users, the manufacturing process is becoming finer and denser, making chips more susceptible to defects. Today’s very deep-submicron semiconductor technologies (0.13 micron and below) have reached susceptibility levels that put conventional semiconductor manufacturing at an impasse. Being able to rapidly develop, manufacture, test, diagnose and verify such complex new chips and products is crucial for the continued success of our economy at-large. This trend is expected to continue at least for the next ten years making possible the design and production of 100 million transistor chips. To speed up the research, the National Technology Roadmap for Semiconductors identified in 1997 a number of major hurdles to be overcome. Some of these hurdles are related to test and dependability. Test is one of the most critical tasks in the semiconductor production process where Integrated Circuits (ICs) are tested several times starting from the wafer probing to the end of production test. Test is not only necessary to assure fault free devices but it also plays a key role in analyzing defects in the manufacturing process. This last point has high relevance since increasing time-to-market pressure on semiconductor fabrication often forces foundries to start volume production on a given semiconductor technology node before reaching the defect densities, and hence yield levels, traditionally obtained at that stage. The feedback derived from test is the only way to analyze and isolate many of the defects in today’s processes and to increase process’s yield. With the increasing need of high quality electronic products, at each new physical assembly level, such as board and system assembly, test is used for debugging, diagnosing and repairing the sub-assemblies in their new environment. Similarly, the increasing reliability, availability and serviceability requirements, lead the users of high-end products performing periodic tests in the field throughout the full life cycle. To allow advancements in each one of the above scaling trends, fundamental changes are expected to emerge in different Integrated Circuits (ICs) realization disciplines such as IC design, packaging and silicon process. These changes have a direct impact on test methods, tools and equipment. Conventional test equipment and methodologies will be inadequate to assure high quality levels. On chip specialized block dedicated to test, usually referred to as Infrastructure IP (Intellectual Property), need to be developed and included in the new complex designs to assure that new chips will be adequately tested, diagnosed, measured, debugged and even sometimes repaired. In this thesis, some of the scaling trends in designing new complex SoCs will be analyzed one at a time, observing their implications on test and identifying the key hurdles/challenges to be addressed. The goal of the remaining of the thesis is the presentation of possible solutions. It is not sufficient to address just one of the challenges; all must be met at the same time to fulfill the market requirements