Parallel Desynchronized Block Matching: A Feasible Scheduling Algorithm for the Input-Buffered Wavelength-Routed Switch

The input-buffered wavelength-routed (IBWR) switch is a promising switching architecture for slotted optical packet switching (OPS) networks. The benefits of the IBWR fabric are a better scalability and lower hardware cost, when compared to output buffered OPS proposals. A previous work characterized the scheduling problem of this architecture as a type of matching problem in bipartite graphs. This characterization establishes an interesting relation between the IBWR scheduling and the scheduling of electronic virtual output queuing switches. In this paper, this relation is further explored, for the design of feasible IBWR scheduling algorithms, in terms of hardware implementation and execution time. As a result, the parallel desynchronized block matching (PDBM) algorithm is proposed. The evaluation results presented reveal that IBWR switch performance using the PDBM algorithm is close to the performance bound given by OPS output buffered architectures. The performance gap is especially small for dense wavelength division multiplexing (DWDM) architectures.This research has been funded by the Spanish MCyT grant TEC2004-05622-C04-02/TCM (ARPaq). Authors would like to thank also the COST 291 action and the e-Photon/ONe+ European Network of Excellence

Survey of switching techniques in high-speed networks and their performance

One of the most promising approaches for high speed networks for integrated service applications is fast packet switching, or ATM (Asynchronous Transfer Mode). ATM can be characterized by very high speed transmission links and simple, hard wired protocols within a network. To match the transmission speed of the network links, and to minimize the overhead due to the processing of network protocols, the switching of cells is done in hardware switching fabrics in ATM networks.A number of designs has been proposed for implementing ATM switches. While many differences exist among the proposals, the vast majority of them is based on self-routing multi-stage interconnection networks. This is because of the desirable features of multi-stage interconnection networks such as self-routing capability and suitability for VLSI implementation.Existing ATM switch architectures can be classified into two major classes: blocking switches, where blockings of cells may occur within a switch when more than one cell contends for the same internal link, and non-blocking switches, where no internal blocking occurs. A large number of techniques has also been proposed to improve the performance of blocking and nonblocking switches. In this paper, we present an extensive survey of the existing proposals for ATM switch architectures, focusing on their performance issues

Architecture, design, and modeling of the OPSnet asynchronous optical packet switching node

An all-optical packet-switched network supporting multiple services represents a long-term goal for network operators and service providers alike. The EPSRC-funded OPSnet project partnership addresses this issue from device through to network architecture perspectives with the key objective of the design, development, and demonstration of a fully operational asynchronous optical packet switch (OPS) suitable for 100 Gb/s dense-wavelength-division multiplexing (DWDM) operation. The OPS is built around a novel buffer and control architecture that has been shown to be highly flexible and to offer the promise of fair and consistent packet delivery at high load conditions with full support for quality of service (QoS) based on differentiated services over generalized multiprotocol label switching

Survey of unified approaches to integrated-service networks

The increasing demand for communication services, coupled with recent technological advances in communication media and switching techniques, has resulted in a proliferation of new and expanded services. Currently, networks are needed which can transmit voice, data, and video services in an application-independent fashion. Unified approaches employ a single switching technique across the entire network bandwidth, thus, allowing services to be switched in an application-independent manner. This paper presents a taxonomy of integrated-service networks including a look at N-ISDN, while focusing on unified approaches to integrated-service networks.The two most promising unified approaches are burst and fast packet switching. Burst switching is a circuit switching-based approach which allocates channel bandwidth to a connection only during the transmission of "bursts" of information. Fast packet switching is a packet switching-based approach which can be characterized by very high transmission rates on network links and simple, hardwired protocols which match the rapid channel speed of the network. Both approaches are being proposed as possible implementations for integrated-service networks. We survey these two approaches, and also examine the key performance issues found in fast packet switching. We then present the results of a simulation study of a fast packet switching network