Timing verification of dynamically reconfigurable logic for Xilinx Virtex FPGA series

This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standard hardware design and verification tools to the design of dynamically reconfigurable logic (DRL). The technique involves the conversion of a dynamic design into multiple static designs, suitable for input to standard synthesis and APR tools. For timing and functional verification after APR, the sections of the design can then be recombined into a single dynamic system. The technique has been automated by extending an existing DRL design tool named DCSTech, which is part of the Dynamic Circuit Switching (DCS) CAD framework. The principles behind the tools are generic and should be readily extensible to other architectures and CAD toolsets. Implementation of the dynamic system involves the production of partial configuration bitstreams to load sections of circuitry. The process of creating such bitstreams, the final stage of our design flow, is summarized

Design Of Fpga Address Register In 28nm Process Technology Based On Standard Cell Based Approach

Secara tradisinya, “Field Programmable Gate Array” (FPGA) “Address Register” (AR) direka menggunakan “full custom”. Dengan keadaan geometri yang mengecut pada awal proses nod, maka keperluan untuk menimbang semula pendekatan reka bentuk yang digunakan untuk mereka bentuk FPGA AR diperlukan kerana kitaran reka bentuk meningkat dan merumitkan yang membawa kepada masa lelaran lanjut ke atas penutupan masa blok. Terdapat pelbagai jenis cabaran yang terpaksa dihadapi dalam proses 28nm dan seterusnya sekiranya pendekatan “full custom” masih digunakan untuk merekabentuk FPGA AR. Oleh itu, pendekatan berasaskan sel piawai digunakan untuk reka bentuk FPGA AR. Kitaran reka bentuk FPGA AR dapat dikurangkan dari bulan ke minggu dengan penggunaan kaedah sel piawai. Selain itu, penutupan masa dapat mengawal senario masa yang lebih. Keputusan menunjukkan bahawa FPGA AR menggunakan pendekatan berasaskan sel piawai adalah memenuhi spesifikasi reka bentuk yang diberikan. Di samping itu, jatuhan IR untuk kuasa dan bumi adalah di bawah 2mV, frekuensi adalah 330 MHz dan keluasan kawasan adalah 0.975mm2. Sebagai kesimpulan, pendekatan berasaskan sel piawai memberi pereka lebih banyak masa untuk menyelesaikan isu yang berkaitan dengan rekabentuk. Di samping itu, perubahan yang disebabkan oleh proses, voltan dan suhu dapat diperbaiki melalui kaedah pelbagai sudut dan senario ke atas FPGA AR. ________________________________________________________________________________________________________________________ Traditionally, Field Programmable Gate Array (FPGA) Address Register (AR) is designed using full custom approach. With geometries shrink on advance process node, there is a need to reconsider the design approach used to design FPGA AR because of increased design cycle and complexity that lead to more iteration time on closing block timing. Significant design effort and challenges are required in 28nm and beyond when using full custom approach. Therefore, standard cell based approach is used to design the FPGA AR. Design cycle of FPGA AR is reduced from months to weeks with the automated standard cell based approach. Besides that, timing closure is able to cover more timing scenarios. Results show that FPGA AR using standard cell based approach is meeting the given design specification. IR drop on both power and ground is achieving less than 2mV per rail, frequency of 330MHz is obtained on FPGA AR and area size is 0.975mm2. In summary, standard cell based approach gives designer more time to focus on resolving design issues, and close the design in more timing scenarios which cover more design corners to improve variation due to process, voltage and temperature

Programmable flexible cores for SoC applications

Tese de mestrado. Engenharia Electrotécnica e de Computadores. Faculdade de Engenharia. Universidade do Porto. 200

Innovative teaching of IC design and manufacture using the Superchip platform

In this paper we describe how an intelligent chip architecture has allowed a large cohort of undergraduate students to be given effective practical insight into IC design by designing and manufacturing their own ICs. To achieve this, an efficient chip architecture, the “Superchip”, has been developed, which allows multiple student designs to be fabricated on a single IC, and encapsulated in a standard package without excessive cost in terms of time or resources. We demonstrate how the practical process has been tightly coupled with theoretical aspects of the degree course and how transferable skills are incorporated into the design exercise. Furthermore, the students are introduced at an early stage to the key concepts of team working, exposure to real deadlines and collaborative report writing. This paper provides details of the teaching rationale, design exercise overview, design process, chip architecture and test regime