Advanced analog layout design automation in compliance with density uniformity

To fabricate a reliable integrated circuit chip, foundries follow specific design rules and layout processing techniques. One of the parameters, which affect circuit performance and final electronic product quality, is the variation of thickness for each semiconductor layer within the fabricated chips. The thickness is closely dependent on the density of geometric features on that layer. Therefore, to ensure consistent thickness, foundries normally have to seriously control distribution of the feature density on each layer by using post-processing operations. In this research, the methods of controlling feature density distribution on different layers of an analog layout during the process of layout migration from an old technology to a new one or updated design specifications in the same technology have been investigated. We aim to achieve density-uniformity-aware layout retargeting for facilitating manufacturing process in the advanced technologies. This can offer an advantage right to the design stage for the designers to evaluate the effects of applying density uniformity to their drafted layouts, which are otherwise usually done by the foundries at the final manufacturing stage without considering circuit performance. Layout modification for density uniformity includes component position change and size modification, which may induce crosstalk noise caused by extra parasitic capacitance. To effectively control this effect, we have also investigated and proposed a simple yet accurate analytic method to model the parasitic capacitance on multi-layer VLSI chips. Supported by this capacitance modeling research, a unique methodology to deal with density-uniformity-aware analog layout retargeting with the capability of parasitic capacitance control has been presented. The proposed operations include layout geometry position rearrangement, interconnect size modification, and extra dummy fill insertion for enhancing layout density uniformity. All of these operations are holistically coordinated by a linear programming optimization scheme. The experimental results demonstrate the efficacy of the proposed methodology compared to the popular digital solutions in terms of minimum density variation and acute parasitic capacitance control

トランジスタ・アレイ方式に基づくアナログレイアウトにおける密度最適化

In integrated circuit design of advanced technology nodes, layout density uniformity significantly influences the manufacturability due to the CMP variability. In analog design, especially, designers are suffering from passing the density checking since there are few useful tools. To tackle this issue, we focus on a transistor-array(TA)-style analog layout, and propose a density optimization algorithm consistent with complicated design rules. Based on TA-style, we introduce a density-aware layout format to explicitly control the layout pattern density, and provide the mathematical optimization approach. Hence, a design flow incorporating our density optimization can drastically reduce the design time with fewer iterations. In a design case of an OPAMP layout in a 65nm CMOS process, the result demonstrates that the proposed approach achieves more than 48× speed-up compared with conventional manual layout, meanwhile, it shows a good circuit performance in the post-layout simulation.北九州市立大

Nanoparticle Engineering for Chemical-Mechanical Planarization

Increasing reliance on electronic devices demands products with high performance and efficiency. Such devices can be realized through the advent of nanoparticle technology. This book explains the physicochemical properties of nanoparticles according to each step in the chemical mechanical planarization (CMP) process, including dielectric CMP, shallow trend isolation CMP, metal CMP, poly isolation CMP, and noble metal CMP. The authors provide a detailed guide to nanoparticle engineering of novel CMP slurry for next-generation nanoscale devices below the 60nm design rule. This comprehensive text also presents design techniques using polymeric additives to improve CMP performance

The Characterization Of The Effects Of Stress Concentrations On The Mechanical Behavior Of A Micronic Woven Wire Mesh

Woven structures are steadily emerging as excellent reinforcing components in dualphase composite materials subjected to multiaxial loads, thermal shock, and aggressive reactants in the environment. Metallic woven wire mesh materials display good ductility and relatively high specific strength and specific resilience. While use of this class of materials is rapidly expanding, significant gaps in mechanical behavior classification remain. This thesis works to address the mechanics of material knowledge gap that exists for characterizing the behavior of a metallic woven structure, composed of stainless steel wires on the order of 25 microns in diameter, and subjected to various loading conditions and stress risers. Uniaxial and biaxial tensile experiments, employing Digital Image Correlation (DIC) as a strain measurement tool, are conducted on woven wire mesh specimens incised in various material orientations, and with various notch geometries. Experimental results, supported by an ample analytic modeling effort, indicate that an orthotropic elastic constitutive model is reasonably capable of governing the macro-scale elasticity of the subject material. Also, the Stress Concentration Factor (SCF) associated with various notch geometries is documented experimentally and analytically, and it is shown that the degree of stress concentration is dependent on both notch and material orientation. The Finite Element Method (FEM) is employed on the macro-scale to expand the experimental test matrix, and to judge the effects of a homogenization assumption when modeling metallic woven structures. Additionally, plasticity of the stainless steel woven wire mesh is considered through experimental determination of the yield surface, and a thorough analytic modeling effort resulting in a modified form of the Hill yield criterion. Finally, mesoscale plasticity of the woven structure is considered, and the form of a multi-scale failure criterion is proposed and exercised numerically

Self-Aligned 3D Chip Integration Technology and Through-Silicon Serial Data Transmission

The emerging three-dimensional (3D) integration technology is expected to lead to an industry paradigm shift due to its tremendous benefits. Intense research activities are going on about technology, simulation, design, and product prototypes. This thesis work aims at fabricating through-silicon vias (TSVs) on diced processor chips, and later bonding them into a 3D-stacked chip. How to handle and process delicate processor chips with high alignment precision is a key issue. The TSV process to be developed also needs to adapt to this constraint. Four TSV processes have been studied. Among them, the ring-trench TSV process demonstrates the feasibility of fabricating TSVs with the prevailing dimensions, and the whole-through TSV process achieves the first dummy chip post-processed with TSVs in EPFL although the dimension is rather large to keep a reasonable aspect ratio (AR). Four self-alignment (SA) techniques have been investigated, among which the gravitational SA and the hydrophobic SA are found to be quite promising. Using gravitational SA, we come to the conclusion that cavities in silicon carrier wafer with a profile angle of 60° can align the chips with less than 20 µm inaccuracies. The alignment precision can be improved after adopting more advanced dicing tools instead of using the traditional dicing saws and larger cavity profile angle. Such inaccuracy will be sufficient to align the relatively large TSVs for general products such as 3D image sensors. By fabricating bottom TSVs in the carrier wafer, a 3D silicon interposer idea has been proposed to stack another chip, e.g. a processor chip, on the other side of the carrier wafer. But stacking microprocessor chips fabricated with TSVs will require higher alignment precision. A hydrophobic SA technique using the surface tension force generated by the water-to-air interfaces around the pads can greatly reduce the alignment inaccuracy to less than 1 µm. This low-cost and high throughput SA procedure is processed in air, fully-compatible with current fabrication technologies, and highly stable and repeatable. We present a theoretical meniscus model to predict SA results and to provide the design rules. This technique is quite promising for advanced 3D applications involving logic and heterogeneous stacking. As TSVs' dimensions in the chip-level 3D integration are constrained by the chip-level processes, such as bonding, the smallest TSVs might still be about 5 µm. Thus, the area occupied by the TSVs cannot be neglected. Fortunately, TSVs can withstand very high bandwidths, meaning that data can be serialized and transmitted using less numbers of TSVs. With 20 µm TSVs, the 2-Gb/s 8:1 serial link implemented saves 75% of the area of its 8-bit parallel counterpart. The quasi-serial link proposed can effectively balance the inter-layer bandwidth and the serial links' area consumption. The area model of the serial or quasi-serial links working under higher frequencies provides some guidelines to choose the proper serial link design, and it also predicts that when TSV diameter shrinks to 5 µm, it will be difficult to keep this area benefit if without some novel circuit design techniques. As the serial links can be implemented with less area, the bandwidth per unit area is increased. Two scenarios are studied, single-port memory access and multi-port memory access. The expanded inter-layer bandwidth by serialization does not improve the system performance because of the bus-bottleneck problem. In the latter scenario, the inter-layer ultra-wide bandwidth can be exploited as each memory bank can be accessed randomly through the NoC. Thus further widening the inter-layer bandwidth through serialization, the system performance will be improved

Effects of scaling on microstructure evolution of Cu nanolines and impact on electromigration reliability

textScaling can significantly degrade the electromigration (EM) lifetime for Cu interconnects, raising serious reliability concerns. Different methods have emerged to enhance the EM resistance of Cu by suppressing the interface diffusion (the historically fastest diffusion path), notably using CoWP metal cap and Mn alloying. With further scaling of Cu interconnects, EM reliability becomes increasingly complex due to changes in Cu microstructure. In ultra-fine Cu lines a large population of small grains mix with bamboo-type grains, resulting in an additional contribution of grain boundary diffusion to EM degradation. With the interface diffusion suppressed by CoWP or Mn alloying, the grain structure effect becomes even more important. The objective of this study is to investigate the EM reliability of ultra-fine Cu interconnects, focusing on the scaling effect on grain structure and mass transport. First, the detailed microstructure information of Cu interconnects down to the 22 nm node was analyzed using a transmission electron microscope (TEM)-based high resolution diffraction technique. A dominant sidewall growth of {111} grains was observed for 70 nm Cu lines (45 nm node), reflecting the importance of interfacial energy in controlling grain growth. The strength of the {111} texture was found to significantly increase as line width was reduced to 40 nm (22 nm node), while the length fraction of coherent twin boundaries was reduced to ~1%. Secondly, the results from microstructure together with the deduced interfacial and grain boundary diffusivities were used to identify flux divergent sites for void formation and to analyze the grain structure effect on EM statistics using a microstructure-based kinetic model. Finally, based on the analysis of Cu grain structure evolution with downscaling, the scaling behavior of EM drift velocity was investigated for Cu interconnects with CoWP capping and Mn alloying. This enables us to project the EM lifetime and statistics for future technology nodes. The Mn alloying effect on mass transport in combination of grain structure control was found to provide an effective means to improve EM reliability especially with further scaling. In summary, this study establishes a correlation between the microstructure of Cu nanolines, void formation kinetics, and EM statistics.Mechanical Engineerin

Design of a high-speed, meso-scale nanopositioners driven by electromagnetic actuators

Thesis (Ph. D.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, 2008.Includes bibliographical references (p. 218-230).The purpose of this thesis is to generate the design and fabrication knowledge that is required to engineer high-speed, six-axis, meso-scale nanopositioners that are driven by electromagnetic actuators. When compared to macro-scale nanopositioners, meso-scale nanopositioners enable a combination of greater bandwidth, improved thermal stability, portability, and capacity for massively parallel operation. Meso-scale nanopositioners are envisioned to impact emerging applications in data storage and nanomanufacturing, which will benefit from low-cost, portable, multi-axis nanopositioners that may position samples with nanometer-level precision at bandwidth of 100s of Hz and over a working envelope greater than 10x10x10 micrometers3 This thesis forms the foundation of design and fabrication knowledge required to engineer mesoscale systems to meet these needs.The design combines a planar silicon flexure bearing and unique moving-coil microactuators that employ millimeter-scale permanent magnets and stacked, planar-spiral micro-coils. The new moving-coil actuator outperforms previous coil designs as it enables orthogonal and linear force capability in two axes while minimizing parasitic forces. The system performance was modeled in the structural, thermal, electrical, and magnetic domains with analytical and finite-element techniques. A new method was created to model the three-dimensional permanent magnet fields of finite magnet arrays. The models were used to optimize the actuator coil and flexure geometry in order to achieve the desired motions, stiffness, and operating temperature, and to reduce thermal error motions.A new microfabrication process and design-for-manufacturing rules were generated to integrate multilayer actuator coils and silicon flexure bearings. The process combines electroplating for the copper coils, a silicon dioxide interlayer dielectric, and deep reactive-ion etching for the silicon flexures and alignment features.(cont.) Microfabrication experiments were used to formulate coil geometry design rules that minimized the delamination and cracking of the materials that comprise the coil structure. Experiments were also used to measure the previously-unreported breakdown strength of the unannealed, PECVD silicon dioxide interlayer dielectric. The results of this research were used to design and fabricate a meso-scale nanopositioner system. The nanopositioner was measured to have a range of motion of 10 micrometers in the lateral directions, a range of 2 micrometers in the out-of-plane direction, an angular range of 0.5 degrees, and a first mode resonant frequency at 900 Hz. Open-loop calibration has been shown to minimize parasitic in-plane motion to less than 100 nm over the range of motion.by Dariusz S. Golda.Ph.D

Solid State Circuits Technologies

The evolution of solid-state circuit technology has a long history within a relatively short period of time. This technology has lead to the modern information society that connects us and tools, a large market, and many types of products and applications. The solid-state circuit technology continuously evolves via breakthroughs and improvements every year. This book is devoted to review and present novel approaches for some of the main issues involved in this exciting and vigorous technology. The book is composed of 22 chapters, written by authors coming from 30 different institutions located in 12 different countries throughout the Americas, Asia and Europe. Thus, reflecting the wide international contribution to the book. The broad range of subjects presented in the book offers a general overview of the main issues in modern solid-state circuit technology. Furthermore, the book offers an in depth analysis on specific subjects for specialists. We believe the book is of great scientific and educational value for many readers. I am profoundly indebted to the support provided by all of those involved in the work. First and foremost I would like to acknowledge and thank the authors who worked hard and generously agreed to share their results and knowledge. Second I would like to express my gratitude to the Intech team that invited me to edit the book and give me their full support and a fruitful experience while working together to combine this book

Electronics for Sensors

The aim of this Special Issue is to explore new advanced solutions in electronic systems and interfaces to be employed in sensors, describing best practices, implementations, and applications. The selected papers in particular concern photomultiplier tubes (PMTs) and silicon photomultipliers (SiPMs) interfaces and applications, techniques for monitoring radiation levels, electronics for biomedical applications, design and applications of time-to-digital converters, interfaces for image sensors, and general-purpose theory and topologies for electronic interfaces