Phase conjugation method and apparatus for an active retrodirective antenna array

An active retrodirective antenna array wherein a reference array element is used to generate a phase reference which is replicated at succeeding elements of the array. Each element of the array is associated with a phase regeneration circuit and the phase conjugation circuitry of an adjacent element. In one implementation, the phase reference circuit operates on the input signal at the reference element, a voltage controlled oscillator (VCO) output signal and the input pilot signal at the next array element received from a transmission line. By proper filtering and mixing, a phase component may be produced to which the VCO may be locked to produce the phase conjugate of the pilot signal at the next array element plus a transmission line delay. In another implementation, particularly suited for large arrays in space, two different input pilot frequencies are employed

A 6.0-mW 10.0-Gb/s Receiver With Switched-Capacitor Summation DFE

A low-power receiver with a one-tap decision feedback equalization (DFE) was fabricated in 90-nm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition at the front-end sample-hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation. A quarter-rate-clocking scheme facilitates the use of low-power front-end circuitry and CMOS clock buffers. The receiver was tested over channels with different levels of ISI. The signaling rate with BER<10^-12 was significantly increased with the use of DFE for short- to medium-distance PCB traces. At 10-Gb/s data rate, the receiver consumes less than 6.0 mW from a 1.0-V supply. This includes the power consumed in all quarter-rate clock buffers, but not the power of a clock recovery loop. The input clock phase and the DFE taps are adjusted externally

A low-power receiver with switched-capacitor summation DFE

A low power receiver with a one tap DFE was fabricated in 90mm CMOS technology. The speculative equalization is performed using switched-capacitor-based addition directly at the front-end sample-hold circuit. In order to further reduce the power consumption, an analog multiplexer is used in the speculation technique implementation. A quarter-rate-clocking scheme facilitates the use of low-power front-end circuitry and CMOS clock buffers. At 10Gb/s data rate, the receiver consumes less than 6.0mW from a 1.0V supply

Frequency translating phase conjugation circuit for active retrodirective antenna array

An active retrodirective antenna array which has central phasing from a reference antenna element through a "tree" structured network of transmission lines utilizes a number of phase conjugate circuits (PCCs) at each node and a phase reference regeneration circuit (PRR) at each node except the initial node. Each node virtually coincides with an element of the array. A PCC generates the exact conjugate phase of an incident signal using a phase locked loop which combines the phases in an up converter, divides the sum by 2 and mixes the result with the phase in a down converter for phase detection. The PRR extracts the phase from the conjugate phase. Both the PCC and the PRR are not only exact but also free from mixer degeneracy

Universal Three Dimensional Optical Logic

Modern integrated circuits are essentially two-dimensional (2D). Partial three-dimensional (3D) integration and 3D-transistor-level integrated circuits have long been anticipated as routes to improve the performance, cost and size of electronic computing systems. Even as electronics approach fundamental limits however, stubborn challenges in 3D circuits, and innovations in planar technology have delayed the dimensional transition. Optical computing offers potential for new computing approaches, substantially greater performance and would complement technologies in optical interconnects and data storage. Nevertheless, despite some progress, few proposed optical transistors possess essential features required for integration into real computing systems. Here we demonstrate a logic gate based on universal features of nonlinear wave propagation: spatiotemporal instability and collapse. It meets the scaling criteria and enables a 3D, reconfigurable, globally-hyperconnected architecture that may achieve an exponential speed up over conventional platforms. It provides an attractive building block for future optical computers, where its universality should facilitate flexible implementations.Comment: manuscript (5 pages, 3 figures) with supplementary information (6 pages, 5 figures

An Offset Cancelation Technique for Latch Type Sense Amplifiers

An offset compensation technique for a latch type sense amplifier is proposed in this paper. The proposed scheme is based on the recalibration of the charging/discharging current of the critical nodes which are affected by the device mismatches. The circuit has been designed in a 65 nm CMOS technology with 1.2 V core transistors. The auto-calibration procedure is fully digital. Simulation results are given verifying the operation for sampling a 5 Gb/s signal dissipating only 360 uW

A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects

Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm^2

Adaptive Nonlinear RF Cancellation for Improved Isolation in Simultaneous Transmit-Receive Systems

This paper proposes an active radio frequency (RF) cancellation solution to suppress the transmitter (TX) passband leakage signal in radio transceivers supporting simultaneous transmission and reception. The proposed technique is based on creating an opposite-phase baseband equivalent replica of the TX leakage signal in the transceiver digital front-end through adaptive nonlinear filtering of the known transmit data, to facilitate highly accurate cancellation under a nonlinear TX power amplifier (PA). The active RF cancellation is then accomplished by employing an auxiliary transmitter chain, to generate the actual RF cancellation signal, and combining it with the received signal at the receiver (RX) low noise amplifier (LNA) input. A closed-loop parameter learning approach, based on the decorrelation principle, is also developed to efficiently estimate the coefficients of the nonlinear cancellation filter in the presence of a nonlinear TX PA with memory, finite passive isolation, and a nonlinear RX LNA. The performance of the proposed cancellation technique is evaluated through comprehensive RF measurements adopting commercial LTE-Advanced transceiver hardware components. The results show that the proposed technique can provide an additional suppression of up to 54 dB for the TX passband leakage signal at the RX LNA input, even at considerably high transmit power levels and with wide transmission bandwidths. Such novel cancellation solution can therefore substantially improve the TX-RX isolation, hence reducing the requirements on passive isolation and RF component linearity, as well as increasing the efficiency and flexibility of the RF spectrum use in the emerging 5G radio networks.Comment: accepted to IEE