The Product Test Scheduling Problem

This research focused on product test scheduling in the presence of in-process and at-completion inspection constraints. Such testing arises in the context of the manufacture of products that must perform reliably in extreme environmental conditions. Often, these products must receive a certification from prescribed regulatory agencies at the successful completion of a predetermined series of tests. Operational efficiency is enhanced by determining the optimal order and start times of tests so as to minimize the makespan while ensuring that technicians are available when needed to complete in-process and at-completion inspections. We refer to this as the product test scheduling problem. We first formulated a mixed-integer linear programming (MILP) model to identify the optimal solution to this problem and solve it using a commercial optimization package. We also present a genetic algorithm (GA) solution methodology that is implemented and solved in Microsoft Excel. Computational results are presented demonstrating the merits and consistency of the MILP and GA solution approaches across a number of scenarios

Dynamic Test Scheduling for Analog Circuits for Improved Test Quality

Abstract-In this paper, we present an innovative test scheduling method to improve test quality and/or reduce test time for analog circuits. Our dynamic test scheduling approach predicts the fail probability of unmeasured specifications with the aim of passing statistically well-behaved chips early on so as to devote more resources to marginal devices. Results show that for a gain controlled LNA circuit, with 48 specification parameters, it is possible to achieve 67% improvement in test quality for the same test time or 19.2% test time reduction with the same test quality compared to the widely used set cover method

Thermal-Aware Test Scheduling for Core-Based SoC in an Abort-on-First-Fail Test Environment

Long test application time and high temperature have become two major issues of system-on-chip (SoC) test. In order to minimize test application times and avoid overheating during tests, we propose a thermal-aware test scheduling technique for core-based SoC in an abort-on-first-fail (AOFF) test environment. The AOFF environment assumes that the test process is terminated as soon as the first fault is detected, which is usually deployed in volume production test. To avoid high temperature, test sets are partitioned into test sub-sequences which are separated by cooling periods. The proposed test scheduling technique utilizes instantaneous thermal simulation results to guide the partitioning of test sets and to determine the lengths of cooling periods. Experimental results have shown that the proposed technique is efficient to minimize the expected test application time while keeping the temperatures of cores under test below the imposed temperature limit