Three-dimensional micromachined on-chip inductors for high frequency applications

Demands for wireless communication are ever-escalating for consumer and military communication applications. The requirements of portability, more functionality and lower cost have been driving forces toward smaller, more sophisticated and flexible wireless devices with lower power consumption. To meet these requirements, monolithically integrated passive inductors with high Q-factors and high self-resonant frequencies are desirable. Q-factor and self-resonant frequency of an inductor are significantly degraded at high frequencies due to conductor ohmic loss, magnetically induced eddy current in the conductive substrate, and lower self-resonant frequency from capacitance between conductive substrate and conductors. In this dissertation, novel three-dimensional arch-like solenoid and dome-shaped spiral inductors are designed, fabricated, and characterized. MEMS-based fabrication techniques such as copper electroplating through voids in thick SU-8 photoresist molds and EAGLE2100 conformal photoresist molds on sacrificial arch-like or dome-shape SJR5740 photoresist mounds are utilized. An air gap between the inductor and the silicon substrate is used to reduce the degradations of inductor performance. According to the Sonnet electromagnetic simulations, 30 μm air-gap suspension over the substrate is an adequate choice for these inductors. Suspended arch-like solenoid copper inductor has flat bottom conductor connected to arch-like top conductor with an air core in between. This design has only 2 contact points per inductor turn to minimize series resistance. Suspended domeshaped spiral copper inductor is fabricated on a sacrificial photoresist dome with the outer end connected to one probe pad, and the inner end connected to the other probe pad through vias and an air-bridge. The sidewalls of spiral turns in this design overlap less with each other thereby reducing inter-turn capacitances. Fabricated inductors are characterized and modeled at high frequencies from Sparameter measurements. ABCD-parameters, derived from the S-parameters are translated into a simplified physical π-model. The resulting arch-like suspended inductors with 2-5 turns have inductances between 0.62 to 0.79 nH, peak Q-factor values between 15.42 to 17 at peak-Q frequencies between 4.7 GHz to 7.0 GHz, and self-resonant frequencies between 47.6 GHz to 88.6 GHz. The 3-turn dome-shaped spiral inductor has inductance of 3.37 nH, peak Q-factor of 35.9 at 1.65 GHz, and self-resonant frequency at 18.74 GHz

Design Guide for CMOS Process On-Chip 3D Inductor using Thru-Wafer Vias

Three-dimensional (3D) inductors using high aspect ratio (10:1) thru-wafer via (TWV) technology in a complementary metal oxide semiconductor (CMOS) process have been designed, fabricated, and measured. The inductors were designed using 500 μm tall vias with the number of turns ranging from 1 to 20 in both a wide and narrow trace width to space ratios. Radio frequency characterization was studied with emphasis upon de-embedding techniques and resulting effects. The open, short, thru de-embedding (OSTD) technique was used to measure all devices. The highest quality factor (Q) measured was 11.25 at 798MHz for a 1-turn device with a self-resonant frequency (fsr) of 4.4GHz. The largest inductance (L) measured was 45nH on a 20-turn wide trace device with a maximum Q of 4.25 at 732MHz. A 40% reduction in area is achieved by exploiting the TWV technology when compared to planar devices. This technology shows promising results with further development and optimization

Characterization and design of CMOS components for microwave and millimeter wave applications

Ph.DDOCTOR OF PHILOSOPH

Ultra high data rate CMOS FEs

The availability of numerous mm-wave frequency bands for wireless communication has motived the exploration of multi-band and multi-mode integrated components and systems in the main stream CMOS technology. This opportunity has faced the RF designer with the transition between schematic and layout. Modeling the performance of circuits after layout and taking into account the parasitic effects resulting from the layout are two issues that are more important and influential at high frequency design. Performaning measurements using on-wafer probing at 60GHz has its own complexities. The very short wave-length of the signals at mm-wave frequencies makes the measurements very sensitiv to the effective length and bending of the interfaces. This paper presents different 60GHz corner blocks, e.g. Low Noise Amplifier, Zero IF mixer, Phase-Locked Loop, A Dual-Mode Mm-Wave Injection-Locked Frequency Divider and an active transformed power amplifiers implemented in CMOS technologies. These results emphasize the feasibility of the realization 60GHZ integrated components and systems in the main stream CMOS technology

CMOS MESFET Cascode Amplifiers for RFIC Applications

abstract: There is an ever-increasing demand for higher bandwidth and data rate ensuing from exploding number of radio frequency integrated systems and devices. As stated in the Shannon-Hartley theorem, the maximum achievable data rate of a communication channel is linearly proportional to the system bandwidth. This is the main driving force behind pushing wireless systems towards millimeter-wave frequency range, where larger bandwidth is available at a higher carrier frequency. Observing the Moor’s law, highly scaled complementary metal–oxide–semiconductor (CMOS) technologies provide fast transistors with a high unity power gain frequency which enables operating at millimeter-wave frequency range. CMOS is the compelling choice for digital and signal processing modules which concurrently offers high computation speed, low power consumption, and mass integration at a high manufacturing yield. One of the main shortcomings of the sub-micron CMOS technologies is the low breakdown voltage of the transistors that limits the dynamic range of the radio frequency (RF) power blocks, especially with the power amplifiers. Low voltage swing restricts the achievable output power which translates into low signal to noise ratio and degraded linearity. Extensive research has been done on proposing new design and IC fabrication techniques with the goal of generating higher output power in CMOS technology. The prominent drawbacks of these solutions are an increased die area, higher cost per design, and lower overall efficiency due to lossy passive components. In this dissertation, CMOS compatible metal–semiconductor field-effect transistor (MESFETs) are utilized to put forward a new solution to enhance the power amplifier’s breakdown voltage, gain and maximum output power. Requiring no change to the conventional CMOS process flow, this low cost approach allows direct incorporation of high voltage power MESFETs into silicon. High voltage MESFETs were employed in a cascode structure to push the amplifier’s cutoff frequency and unity power gain frequency to the 5G and K-band frequency range. This dissertation begins with CMOS compatible MESFET modeling and fabrication steps, and culminates in the discussion of amplifier design and optimization methodology, parasitic de-embedding steps, simulation and measurement results, and high resistivity RF substrate characterization.Dissertation/ThesisDoctoral Dissertation Electrical Engineering 201

Extension of 0.18µm standard CMOS technology operating range to the microwave and millimetre-wave regime

There is an increasing interest in building millimetre-wave circuits on standard digital complementary metal oxide semiconductor (CMOS) technology for applications such as wireless local area networks (WLAN), automotive radar and remote sensing. This stems from the existing low cost, well-developed, high yield infrastructure for mass production. The overall aim of this thesis is to extend the operating range of 0.18um standard logic CMOS technology to millimetre-wave regime. To this end, microwave and millimetre-wave design, optimisation and modelling methodologies for active and passive devices and low noise circuit implementation are described. As part of the evaluation, new systematic and modular ways of making high performance passive and active devices such as spiral inductors, slow-wave coplanar waveguide (CPW) transmission lines, comb capacitors and NMOS transistors are proposed, designed, simulated, fabricated, modelled and analysed. Small-signal and noise de-embedding techniques are developed and verified up to 110 GHz, providing an increased accuracy in the device model, leading to a robust design at millimetre-wave frequencies. Reduced substrate losses resulting in increased quality factor are presented for optimised spiral inductor designs, featuring patterned floating shield (PFS), enabling improved matching network and a reduced chip area. Based on the proposed shielded slow-wave CPW, both the line attenuation and structure length are decreased, resulting in a more compact and simplified circuit design. An optimised transistor design, aimed at reducing the layout parasitic effects, was realised. The optimisation led to a significant improvement in the gain and noise performance of the transistor, extending its operation beyond the cut-off frequency (ft). By combining all the optimised components, low noise amplifiers (LNAs) operating at 25 GHz and 40 GHz were implemented and compared. These LNAs demonstrate state-of-the-art performance, with the 40 GHz LNA exhibiting the highest gain and lowest noise performance of any LNA reported using 0.18um CMOS technology. On the other hand, the 25 GHz LNA showed a comparable performance to other reported results in literature using several topologies implemented in CMOS technology. These findings will provide a framework for expansion to smaller CMOS technology nodes with the view of extending to sub millimetre-wave frequencies

Ultra high data rate CMOS front ends

The availability of numerous mm-wave frequency bands for wireless communication has motivated the exploration of multi-band and multi-mode integrated components and systems in the main stream CMOS technology. This opportunity has faced the RF designer with the transition between schematic and layout. Modeling the performance of circuits after layout and taking into account the parasitic effects resulting from the layout are two issues that are more important and influential at high frequency design. Performing measurements using on-wafer probing at 60 GHz has its own complexities. The very short wave-length of the signals at mm-wave frequencies makes the measurements very sensitive to the effective length and bending of the interfaces. This paper presents different 60 GHz corner blocks, e.g. Low Noise Amplifier, Zero IF mixer, Phase-Locked Loop, a Dual-Mode Mm-Wave Injection-Locked Frequency Divider and an active transformed power amplifiers implemented in CMOS technologies. These results emphasize the feasibility of the realization 60 GHZ integrated components and systems in the main stream CMOS technology