A procedural method for the efficient implementation of full-custom VLSI designs

An imbedded language system for the layout of very large scale integration (VLSI) circuits is examined. It is shown that through the judicious use of this system, a large variety of circuits can be designed with circuit density and performance comparable to traditional full-custom design methods, but with design costs more comparable to semi-custom design methods. The high performance of this methodology is attributable to the flexibility of procedural descriptions of VLSI layouts and to a number of automatic and semi-automatic tools within the system

A generic operational simulation for early design civil unmanned aerial vehicles

Contemporary aerospace programmes often suffer from large cost overruns, delivery delays and inferior product quality. This is caused in part by poor predictive quality of the early design phase processes with regards to the operational environment of a product. This paper develops the idea of a generic operational simulation that can help designers to rigorously analyse and test their early product concepts. The simulation focusses on civil Unmanned Air Vehicle products and missions to keep the scope of work tractable. The research agenda is introduced along with ideas, initial results and future work. Designers specify details about their product, its environment and anticipated operational procedures. The simulation returns information that can help to estimate the value of the product using the value-driven design approach. Information will include recurring and non-recurring mission cost items. The research aim is to show that an operational simulation can improve early design concepts, thereby reducing delays and cost overruns. Moreover, a trade-off between mission fidelity and model generality is sought along with a generic ontology of civil Unmanned Air Vehicle missions and guidelines about capturing operational informatio

Dynamic Power Management for Neuromorphic Many-Core Systems

This work presents a dynamic power management architecture for neuromorphic many core systems such as SpiNNaker. A fast dynamic voltage and frequency scaling (DVFS) technique is presented which allows the processing elements (PE) to change their supply voltage and clock frequency individually and autonomously within less than 100 ns. This is employed by the neuromorphic simulation software flow, which defines the performance level (PL) of the PE based on the actual workload within each simulation cycle. A test chip in 28 nm SLP CMOS technology has been implemented. It includes 4 PEs which can be scaled from 0.7 V to 1.0 V with frequencies from 125 MHz to 500 MHz at three distinct PLs. By measurement of three neuromorphic benchmarks it is shown that the total PE power consumption can be reduced by 75%, with 80% baseline power reduction and a 50% reduction of energy per neuron and synapse computation, all while maintaining temporary peak system performance to achieve biological real-time operation of the system. A numerical model of this power management model is derived which allows DVFS architecture exploration for neuromorphics. The proposed technique is to be used for the second generation SpiNNaker neuromorphic many core system

Aggregation-Based Feature Invention and Relational

Due to interest in social and economic networks, relational modeling is attracting increasing attention. The field of relational data mining/learning, which traditionally was dominated by logic-based approaches, has recently been extended by adapting learning methods such as naive Bayes, Baysian networks and decision trees to relational tasks. One aspect inherent to all methods of model induction from relational data is the construction of features through the aggregation of sets. The theoretical part of this work (1) presents an ontology of relational concepts of increasing complexity, (2) derives classes of aggregation operators that are needed to learn these concepts, and (3) classifies relational domains based on relational schema characteristics such as cardinality. We then present a new class of aggregation functions, ones that are particularly well suited for relational classification and class probability estimation. The empirical part of this paper demonstrates on real domain the effects on the system performance of different aggregation methods on different relational concepts. The results suggest that more complex aggregation methods can significantly increase generalization performance and that, in particular, task-specific aggregation can simplify relational prediction tasks into well-understood propositional learning problems.Information Systems Working Papers Serie

Deep learning in edge: evaluation of models and frameworks in ARM architecture

The boom and popularization of edge devices have molded its market due to stiff compe tition that provides better functionalities at low energy costs. The ARM architecture has been unanimously unopposed in the huge market segment of smartphones and still makes a presence beyond that: in drones, surveillance systems, cars, and robots. Also, it has been used successfully for the development of solutions for chains that supply food, fuel, and other services. Up until recently, ARM did not show much promise for high-level compu tation, i.e., thanks to its limited RISC instruction set, it was considered power efficient but weak in performance compared to x86 architecture. However, most recent advancements in ARM architecture pivoted that inflection point up thanks to the introduction of embed ded GPUs with DMA into LPDDR memory boards. Since this development in boards such as NVIDIA TK1, NVIDIA Jetson TX1, and NVIDIA TX2, perhaps it finally be came feasible to study and perform more challenging parallel and distributed workloads directly on a RISC-based architecture. On the other hand, the novelty of this technology poses a fundamental question of whether these boards are gaining a meaningful ratio be tween processing power and power consumption over conventional architectures or if they are bound to have reached their limitations. This work explores the Parallel Processing of Deep Learning on embedded GPUs of NVIDIA Jetson TX2 to evaluate the question above comprehensively. Thus, it uses 4 ARM boards, with 2 Deep Learning frameworks, 7 CNN models, and one medium-sized dataset combined into six board settings to con duct experiments. The experiments were conducted under similar environments, all built from the source. Altogether, the experiments ran for a total of 4,804 hours and revealed a slight advantage for MxNet on GPU-reliant training and a PyTorch overall advantage in total execution time and power, but especially for CPU-only executions. The experi ments also showed that the NVIDIA Jetson TX2 already makes feasible some complex workloads directly on its SoC

Design for manufacturing: Performance characterization of digital VLSI systems using a statistical analysis/inference methodology

Design For Manufacturing (DFM) is a TQM methodology by which inherently producible products can be manufactured with high yields, short turnaround time and great flexibility. The key to the success of any DFM program lies in increased accuracy in the modeling of the process and product designs, product simulations and effective manufacturing feedback of key parametric data. That is, properly modeling and simulating designs with data which reflects current fabrication capabilities has the most lasting influence in the performance of products. It is this area that is tackled in the methodology developed hereafter; a method by which to feedback and feedforward parametric data critical to the performance of Digital VLSI systems for performance prediction purposes. In this method, integrated circuit and applied statistics concepts are used jointly to perform analyses and inferences on response variables as a function of key processing and design variables that can be statistically controlled. Furthermore, an experimental design procedure utilizing electrical simulation is proposed to efficiently collect data and test previously proposed hypotheses. Conclusions are finally made with regard to the usefulness and outreach of this method, as well as those areas affected by the behavior of the performance predictors, both in the design and manufacturing stages of VLSI engineering