5,530 research outputs found
Performance Characterization of Multi-threaded Graph Processing Applications on Intel Many-Integrated-Core Architecture
Intel Xeon Phi many-integrated-core (MIC) architectures usher in a new era of
terascale integration. Among emerging killer applications, parallel graph
processing has been a critical technique to analyze connected data. In this
paper, we empirically evaluate various computing platforms including an Intel
Xeon E5 CPU, a Nvidia Geforce GTX1070 GPU and an Xeon Phi 7210 processor
codenamed Knights Landing (KNL) in the domain of parallel graph processing. We
show that the KNL gains encouraging performance when processing graphs, so that
it can become a promising solution to accelerating multi-threaded graph
applications. We further characterize the impact of KNL architectural
enhancements on the performance of a state-of-the art graph framework.We have
four key observations: 1 Different graph applications require distinctive
numbers of threads to reach the peak performance. For the same application,
various datasets need even different numbers of threads to achieve the best
performance. 2 Only a few graph applications benefit from the high bandwidth
MCDRAM, while others favor the low latency DDR4 DRAM. 3 Vector processing units
executing AVX512 SIMD instructions on KNLs are underutilized when running the
state-of-the-art graph framework. 4 The sub-NUMA cache clustering mode offering
the lowest local memory access latency hurts the performance of graph
benchmarks that are lack of NUMA awareness. At last, We suggest future works
including system auto-tuning tools and graph framework optimizations to fully
exploit the potential of KNL for parallel graph processing.Comment: published as L. Jiang, L. Chen and J. Qiu, "Performance
Characterization of Multi-threaded Graph Processing Applications on
Many-Integrated-Core Architecture," 2018 IEEE International Symposium on
Performance Analysis of Systems and Software (ISPASS), Belfast, United
Kingdom, 2018, pp. 199-20
Architecture-Aware Configuration and Scheduling of Matrix Multiplication on Asymmetric Multicore Processors
Asymmetric multicore processors (AMPs) have recently emerged as an appealing
technology for severely energy-constrained environments, especially in mobile
appliances where heterogeneity in applications is mainstream. In addition,
given the growing interest for low-power high performance computing, this type
of architectures is also being investigated as a means to improve the
throughput-per-Watt of complex scientific applications.
In this paper, we design and embed several architecture-aware optimizations
into a multi-threaded general matrix multiplication (gemm), a key operation of
the BLAS, in order to obtain a high performance implementation for ARM
big.LITTLE AMPs. Our solution is based on the reference implementation of gemm
in the BLIS library, and integrates a cache-aware configuration as well as
asymmetric--static and dynamic scheduling strategies that carefully tune and
distribute the operation's micro-kernels among the big and LITTLE cores of the
target processor. The experimental results on a Samsung Exynos 5422, a
system-on-chip with ARM Cortex-A15 and Cortex-A7 clusters that implements the
big.LITTLE model, expose that our cache-aware versions of gemm with asymmetric
scheduling attain important gains in performance with respect to its
architecture-oblivious counterparts while exploiting all the resources of the
AMP to deliver considerable energy efficiency
Improving performance guarantees in wormhole mesh NoC designs
Wormhole-based mesh Networks-on-Chip (wNoC) are deployed in high-performance many-core processors due to their physical scalability and low-cost. Delivering tight and time composable Worst-Case Execution Time (WCET) estimates for applications as needed in safety-critical real-time embedded systems is challenged by wNoCs due to their distributed nature. We propose a bandwidth control mechanism for wNoCs that enables the computation of tight time-composable WCET estimates with low average performance degradation and high scalability. Our evaluation
with the EEMBC automotive suite and an industrial real-time parallel avionics application confirms so.The research leading to these results is funded by the European Union Seventh
Framework Programme under grant agreement no. 287519 (parMERASA)
and by the Ministry of Science and Technology of Spain under contract TIN2012-34557. Milos Panic is funded by the Spanish Ministry of Education under the FPU grant FPU12/05966. Carles Hernández is jointly funded by the
Spanish Ministry of Economy and Competitiveness and FEDER funds through
grant TIN2014-60404-JIN. Jaume Abella is partially supported by the Ministry
of Economy and Competitiveness under Ramon y Cajal postdoctoral fellowship
number RYC-2013-14717.Peer ReviewedPostprint (author's final draft
OS Scheduling Algorithms for Memory Intensive Workloads in Multi-socket Multi-core servers
Major chip manufacturers have all introduced multicore microprocessors.
Multi-socket systems built from these processors are routinely used for running
various server applications. Depending on the application that is run on the
system, remote memory accesses can impact overall performance. This paper
presents a new operating system (OS) scheduling optimization to reduce the
impact of such remote memory accesses. By observing the pattern of local and
remote DRAM accesses for every thread in each scheduling quantum and applying
different algorithms, we come up with a new schedule of threads for the next
quantum. This new schedule potentially cuts down remote DRAM accesses for the
next scheduling quantum and improves overall performance. We present three such
new algorithms of varying complexity followed by an algorithm which is an
adaptation of Hungarian algorithm. We used three different synthetic workloads
to evaluate the algorithm. We also performed sensitivity analysis with respect
to varying DRAM latency. We show that these algorithms can cut down DRAM access
latency by up to 55% depending on the algorithm used. The benefit gained from
the algorithms is dependent upon their complexity. In general higher the
complexity higher is the benefit. Hungarian algorithm results in an optimal
solution. We find that two out of four algorithms provide a good trade-off
between performance and complexity for the workloads we studied
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