On-board beam generation for multibeam satellite systems

This paper aims at designing an onboard beam generation process for a hybrid onboard on-ground multibeam satellite architecture. The proposed method offers a good tradeoff between total throughput and feeder link bandwidth requirements compared with pure on-ground systems. Full frequency reuse among beams is considered, and the beamforming at the satellite is designed for supporting interference mitigation techniques. In addition, in order to reduce the payload cost and complexity, this onboard beamforming is assumed to be constant and the same for forward and return link transmissions so that the same array-fed reflector can be used for forward and return links, leading to a substantial reduction of the payload mass. To meet all these requirements, a novel robust minimum mean square error optimization is conceived. The benefits of the considered scheme are evaluated with respect to the current approaches both analytically and numerically. Indeed, we show that with the DVB-RCS and DVB-S2 standards, our proposal allows increasing the total throughput within a range between 6% and 15% with respect to other onboard processing techniques in the return and forward link, respectively.Peer ReviewedPostprint (author's final draft

Adaptive robust video broadcast via satellite

© 2016 Springer Science+Business Media New YorkWith increasing demand for multimedia content over channels with limited bandwidth and heavy packet losses, higher coding efficiency and stronger error resiliency is required more than ever before. Both the coding efficiency and error resiliency are two opposing processes that require appropriate balancing. On the source encoding side the video encoder H.264/AVC can provide higher compression with strong error resiliency, while on the channel error correction coding side the raptor code has proven its effectiveness, with only modest overhead required for the recovery of lost data. This paper compares the efficiency and overhead of both the raptor codes and the error resiliency techniques of video standards so that both can be balanced for better compression and quality. The result is also improved by confining the robust stream to the period of poor channel conditions by adaptively switching between the video streams using switching frames introduced in H.264/AVC. In this case the video stream is initially transmitted without error resiliency assuming the channel to be completely error free, and then the robustness is increased based on the channel conditions and/or user demand. The results showed that although switching can increase the peak signal to noise ratio in the presence of losses but at the same time its excessive repetition can be irritating to the viewers. Therefore to evaluate the perceptual quality of the video streams and to find the optimum number of switching during a session, these streams were scored by different viewers for quality of enhancement. The results of the proposed scheme show an increase of 3 to 4 dB in peak signal to noise ratio with acceptable quality of enhancement

Implementação de um modulador para DVB-RCS2 em FPGA

Trabalho de Conclusão de Curso (graduação)—Universidade de Brasília, Faculdade UnB Gama, 2019.Este trabalho objetiva implementar em um FPGA as quatro modulações lineares do protocolo DVB-RCS2: \u1d70b/2-BPSK, QPSK, 8PSK e 16QAM, em banda base e usando o filtro formatador de pulsos exigido pela norma, um cosseno levantado com raiz quadrada (SRRC) com fator de roll-off de 0,2. Foram construídos scripts interpretados pelo GNU/Octave para produção de valores de referência, geração de símbolos de teste e comparação dos dados experimentais com os modelos de referência. A quantização dos coeficientes do filtro e dos símbolos usados nas constelações foi feita em ponto fixo, sendo a quantidade de bits determinada através de uma análise de precisão numérica usando o GNU/Octave para comparar o erro quadrático médio entre os valores em ponto flutuante e os quantizados. Um script também foi desenvolvido para automatizar a descrição em VHDL do filtro SRRC a partir dos coeficientes do filtro, dos bits de quantização e do fator de oversample. O funcionamento do sistema descrito em VHDL foi verificado através de simulações comportamentais e da implementação com uma arquitetura com memórias que possuem vetores de teste em um kit de desenvolvimento. As simulações comportamentais do sistema com a arquitetura de testes a uma frequência de operação de 125 MHz informam que o sistema possui latência de 376 ns e taxa de transmissão de símbolos de 17,5 MHz. O modulador e uma arquitetura de testes descritos em VHDL e o hardware de instrumentação, usado para captura de dados, foram implementados em um FPGA XC7Z010-1CLG400C, presente no kit de desenvolvimento Zybo Revisão B a uma frequência de operação de 125 MHz. Verificou-se que o sistema sem o hardware de instrumentação inserido pelo Integrated Logic Analyser (ILA) pode ser implementado a uma frequência de 166,67 MHz, sendo que, na frequência padrão, são consumidos 3921 Look-Up Tables (LUTs), 4547 registradores, 2 memórias em bloco, 38 entradas e saídas, uma linha global de clock e 121 mW de potência. Os dados obtidos pelo ILA foram comparados com os modelos de referência e encontrou-se um erro quadrático médio da ordem de 10−6 para as partes real e imaginária das modulações implementadas.This work intends to implement the four linear modulations employed in the DVB-RCS2 protocol: \u1d70b/2-BPSK, QPSK, 8PSK e 16QAM. The modulations will be implemented in baseband using a Square Root Raised Cosine Filter for pulse formatting with a roll-off factor of 0,2. GNU/Octave scripts were developed for reference values and test vectors generation, and to compare experimentally obtained data with the reference models. The filter coefficients and the constellation symbols were quantised using fixed point. The bit depth used in the quantisation process was determined by a numerical precision analysis that used GNU/Octave to compare the mean square error between the floating-point values and the quantised ones. A script was developed in order to automatise the generation of the VHDL description of the SRRC filter based on its coefficients, the number of bits used for quantisation and the oversample factor. The system was validated using behavioural simulations and one hardware implementation in a development kit. This implementation contains one architecture with memories containing test vectors. The behavioural simulations were performed at a 125 MHz frequency and revealed the system’s latency and symbol transmission rate: 376 ns and 17,5 MHz. The modulator and a test architecture, both described using VHDL, were implemented in a XC7Z010-1CLG400C FPGA contained in the Zybo Rev. B development kit at the operating frequency of 125 MHz. Verifications showed that the system without the instrumentation hardware inserted by the Integrated Logic Analyser (ILA) can be implemented at a 166,67 MHz operating frequency. Running at the standard 125 MHz frequency the system uses 3921 Look-Up Tables (LUTs), 4547 registers, 2 block memories, 38 input and output pins, one global clock buffer and 121 mW of power. The data obtained using the ILA was compared with the reference models and the average quadratic error found was close to 10−6 for the real and imaginary terms of the implemented modulations

Economically sustainable public security and emergency network exploiting a broadband communications satellite

The research contributes to work in Rapid Deployment of a National Public Security and Emergency Communications Network using Communication Satellite Broadband. Although studies in Public Security Communication networks have examined the use of communications satellite as an integral part of the Communication Infrastructure, there has not been an in-depth design analysis of an optimized regional broadband-based communication satellite in relation to the envisaged service coverage area, with little or no terrestrial last-mile telecommunications infrastructure for delivery of satellite solutions, applications and services. As such, the research provides a case study of a Nigerian Public Safety Security Communications Pilot project deployed in regions of the African continent with inadequate terrestrial last mile infrastructure and thus requiring a robust regional Communications Satellite complemented with variants of terrestrial wireless technologies to bridge the digital hiatus as a short and medium term measure apart from other strategic needs. The research not only addresses the pivotal role of a secured integrated communications Public safety network for security agencies and emergency service organizations with its potential to foster efficient information symmetry amongst their operations including during emergency and crisis management in a timely manner but demonstrates a working model of how analogue spectrum meant for Push-to-Talk (PTT) services can be re-farmed and digitalized as a “dedicated” broadband-based public communications system. The network’s sustainability can be secured by using excess capacity for the strategic commercial telecommunication needs of the state and its citizens. Utilization of scarce spectrum has been deployed for Nigeria’s Cashless policy pilot project for financial and digital inclusion. This effectively drives the universal access goals, without exclusivity, in a continent, which still remains the least wired in the world