Miniaturization of on-chip passive electronic devices by silicon nitride self-rolled-up membrane microtube nanotechnology

Miniaturization of the commonly used on-chip lumped elements is highly desirable to enhance the density, performance and functionality of integrated circuits (ICs) working from DC to millimeter wave frequency band. Numerous improvement methods have been demonstrated but all fail to fundamentally solve the intrinsic drawbacks of currently used planar spiral platforms for passive lumped elements. A new design platform based on self-rolled-up membrane (S-RuM) nanotechnology that “processes like 2-D and functions like 3-D” is proposed for constructing on-chip three-dimensional (3-D) rolled-up microtube structures. By taking lumped inductors and transformers, this thesis demonstrates a global solution to obtain on-chip lumped elements with an extremely small on-chip footprint and almost complete immunity to substrate issues. The fabrication process of S-RuM lumped elements is designed to be CMOS compatible with a clear trend to achieving 100% fabrication yield. A quasi-dynamic finite element method (FEM) is established to precisely calculate the dimensions of rolled-up structures, which allows an accurate simulation of the electrical performance of S-RuM lumped passive devices by physical modeling. The design of the S-RuM inductor from FEM structural simulation to physical model electrical simulation is demonstrated, and its physical model is further integrated into the commercial Advanced Design System (ADS) software as a design kit for circuit-level simulation. Full wave FEM 3-D modeling of ICs including S-RuM inductors in the layouts is enabled by EMPro and ADS FEM co-simulation. A simple high pass filter is used as an example to show the S-RuM IC design process. A clear trend to save 38% ~ 50% chip size is also shown in active IC examples by replacing planar spiral inductors with S-RuM inductors. As a unit device, the S-RuM inductor can be used to build other passive elements like transformers. So, the S-RuM transformer is also investigated in this thesis. The thermal and mechanical reliability of the S-RuM platform are tested by using rapid thermal annealing (RTA) and nano-indention, which provide data for further packaging S-RuM lumped passive devices and applications in a power electronics. All samples are fabricated on a 1 to 10 cm p-type silicon substrate. Cu based S-RuM inductor samples show a 119 nH/mm2 inductance density, Q factor of 3 @ 8 GHz, a 0.3 nH to 2.4 nH inductance range, a self-resonant-frequency (SRF) of ~20 GHz, 250 C thermal stability, and 48.6 N/m stiffness. Au based S-RuM transformer samples shows a 1.52:1 turn ratio (n), 0.99 mutual magnetic coupling coefficient (km), and 0.392 maximum available gain at 8.6 GHz with a footprint (S) of only ~0.0085 mm2. The corresponding index of transformer performance ((n∙ km)/S ) is 177, which is ~2 than that of the best on-chip planar transformer reported so far with a similar turn ratio. The performance of the S-RuM transformers is stable at temperatures up to 250 ºC, and the hardness of the rolled-up structures is as high as 270.2 N/m

Modeling and characterization of on-chip interconnects, inductors and transformers

Ph.DNUS-SUPELEC JOINT PH.D. PROGRAMM

Reducing signal coupling and crosstalk in monolithic, mixed-signal integrated circuits

Master of ScienceDepartment of Electrical EngineeringWilliam B. KuhnDesigners of mixed-signal systems must understand coupling mechanisms at the system, PC board, package and integrated circuit levels to control crosstalk, and thereby minimize degradation of system performance. This research examines coupling mechanisms in a RF-targeted high-resistivity partially-depleted Silicon-on-Insulator (SOI) IC process and applying similar coupling mitigation strategies from higher levels of design, proposes techniques to reduce coupling between sub-circuits on-chip. A series of test structures was fabricated with the goal of understanding and reducing the electric and magnetic field coupling at frequencies up to C-Band. Electric field coupling through the active-layer and substrate of the SOI wafer is compared for a variety of isolation methods including use of deep-trench surrounds, blocking channel-stopper implant, blocking metal-fill layers and using substrate contact guard-rings. Magnetic coupling is examined for on-chip inductors utilizing counter-winding techniques, using metal shields above noisy circuits, and through the relationship between separation and the coupling coefficient. Finally, coupling between bond pads employing the most effective electric field isolation strategies is examined. Lumped element circuit models are developed to show how different coupling mitigation strategies perform. Major conclusions relative to substrate coupling are 1) substrates with resistivity 1 kΩ·cm or greater act largely as a high-K insulators at sufficiently high frequency, 2) compared to capacitive coupling paths through the substrate, coupling through metal-fill has little effect and 3) the use of substrate contact guard-rings in multi-ground domain designs can result in significant coupling between domains if proper isolation strategies such as the use of deep-trench surrounds are not employed. The electric field coupling, in general, is strongly dependent on the impedance of the active-layer and frequency, with isolation exceeding 80 dB below 100 MHz and relatively high coupling values of 40 dB or more at upper S-band frequencies, depending on the geometries and mitigation strategy used. Magnetic coupling was found to be a strong function of circuit separation and the height of metal shields above the circuits. Finally, bond pads utilizing substrate contact guard-rings resulted in the highest degree of isolation and the lowest pad load capacitance of the methods tested

Self-rolled-up membrane (S-RuM) capacitors and filters for radio frequency communication

Self-rolled-up membrane (S-RuM) is a novel technology to build precisely controllable three- dimensional (3D) micro-structures. This technology finds wide applications in passive electronics, photonics, and neural interfaces, and achieves great device size reduction and performance enhancement. For passive electronics, devices based on S-RuM utilize electromagnetic energy well- confined in the device tubular cavity with extremely high efficiency, and break the footprint and parasitic effect limit set by conventional planar devices. S-RuM inductors and capacitors can reach self- resonant frequency up to 60 GHz, Q factor up to 80, and with footprint one hundredth that of the state- of-the-art 2D counterparts. This thesis illustrates the working mechanism of S-RuM technology first, and then introduces S-RuM passive electronic devices for radio frequency (RF) application. Current approaches to improve RF passive device performance are discussed. Designs of capacitors and filters based on S-RuM are demonstrated, followed by simulation and lab measurement results. Challenges associated with S-RuM passive electronics are addressed and solutions are proposed. Future work and potential wearable device applications are summarized

Signaling in 3-D integrated circuits, benefits and challenges

Three-dimensional (3-D) or vertical integration is a design and packaging paradigm that can mitigate many of the increasing challenges related to the design of modern integrated systems. 3-D circuits have recently been at the spotlight, since these circuits provide a potent approach to enhance the performance and integrate diverse functions within amulti-plane stack. Clock networks consume a great portion of the power dissipated in a circuit. Therefore, designing a low-power clock network in synchronous circuits is an important task. This requirement is stricter for 3-D circuits due to the increased power densities. Synchronization issues can be more challenging for 3-D circuits since a clock path can spread across several planes with different physical and electrical characteristics. Consequently, designing low power clock networks for 3-D circuits is an important issue. Resonant clock networks are considered efficient low-power alternatives to conventional clock distribution schemes. These networks utilize additional inductive circuits to reduce power while delivering a full swing clock signal to the sink nodes. In this research, a design method to apply resonant clocking to synthesized clock trees is proposed. Manufacturing processes for 3-D circuits include some additional steps as compared to standard CMOS processes which makes 3-D circuits more susceptible to manufacturing defects and lowers the overall yield of the bonded 3-D stack. Testing is another complicated task for 3-D ICs, where pre-bond test is a prerequisite. Pre-bond testability, in turn, presents new challenges to 3-D clock network design primarily due to the incomplete clock distribution networks prior to the bonding of the planes. A design methodology of resonant 3-D clock networks that support wireless pre-bond testing is introduced. To efficiently address this issue, inductive links are exploited to wirelessly transmit the clock signal to the disjoint resonant clock networks. The inductors comprising the LC tanks are used as the receiver circuit for the links, essentially eliminating the need for additional circuits and/or interconnect resources during pre-bond test. Recent FPGAs are quite complex circuits which provide reconfigurablity at the cost of lower performance and higher power consumption as compared to ASIC circuits. Exploiting a large number of programmable switches, routing structures are mainly responsible for performance degradation in FPAGs. Employing 3-D technology can providemore efficient switches which drastically improve the performance and reduce the power consumption of the FPGA. RRAM switches are one of the most promising candidates to improve the FPGA routing architecture thanks to their low on-resistance and non-volatility. Along with the configurable switches, buffers are the other important element of the FPGAs routing structure. Different characteristics of RRAM switches change the properties of signal paths in RRAM-based FPGAs. The on resistance of RRAMswitches is considerably lower than CMOS pass gate switches which results in lower RC delay for RRAM-based routing paths. This different nature in critical path and signal delay in turn affect the need for intermediate buffers. Thus the buffer allocation should be reconsidered. In the last part of this research, the effect of intermediate buffers on signal propagation delay is studied and a modified buffer allocation scheme for RRAM-based FPGA routing path is proposed

Low Temperature RF MEMS Inductors Using Porous Anodic Alumina

In today’s communication devices, the need for high performance inductors is increasing as they are extensively used in RF integrated circuits (RFICs). This need is even more pronounced for variable inductors as they are widely required in tunable filters, voltage controlled amplifiers (VCO) and low noise amplifiers (LNA). For RFICs, the main tuning elements are solid state varactors that are used in conjunction with invariable inductors. However, they have limited linearity, high resistive losses, and low self resonant frequencies. This emphasizes the need for developing another tuning element that can be fabricated monolithically with ICs and can offer high range of tuning. Due to the ease of CMOS integration and low cost silicon based IC fabrication, the inductors currently used are a major source of energy loss, therefore driving the overall quality factor and performance of the chip down. During the last decade there has been an increase in research in RF MicroelectroMechanical Systems (RF MEMS) to develop high quality on chip tunable RF components. MEMS capacitors were initially proposed to substitute the existing varactors, however they can not be easily integrated on top of CMOS circuits. RF MEMS variable inductors have recently attracted attention as a better alternative. The research presented here explores using porous anodic alumina (PAA) in CMOS and MEMS fabrication. Due to its low cost and low temperature processing, PAA is an excellent candidate for silicon system integration. At first, PAA is explored as an isolation layer between the inductor and the lossy silicon substrate. Simulations show that although the dielectric constant of the PAA is tunable, the stress produced by the required thicker layers is problematic. Nevertheless, the use of PAA as a MEMS material shows much more promise. Tunable RF MEMS inductors based on bimorph sandwich layer of aluminum PAA and aluminum are fabricated and tested. A tuning range of 31% is achieved for an inductance variation of 5.8 nH to 7.6 nH at 3 GHz. To further improve the Q, bimorph layers of gold and PAA are fabricated on Alumina substrates. A lower tuning range is produced; however the quality factor performance is greatly improved. A peak Q of over 30 with a demonstrated 3% tuning range is presented. Depending on the need for either high performance or tunability, two types of tunable RF MEMS inductors are presented. Although PAA shows promise as a mechanical material for MEMS, the processing parameters (mainly stress and loss tangent) need to be improved if used as an isolation layer. To our knowledge, this is the first time this material has been proposed and successfully used as a structural material for MEMS devices and CMOS processes