Layout to circuit extraction for three-dimensional thermal-electrical circuit simulation of device structures

In this paper, a method is proposed for extraction of coupled networks from layout information for simulation of electrothermal device behavior. The networks represent a three-dimensional (3-D) device structure with circuit elements. The electrical and thermal characteristics of this circuit representation are calculated with a circuit simulator. Spatial potential distributions, current flows, and temperature distributions in the device structure are calculated on the spatial coordinates. This simulation method can be placed between device simulation and (conventional) circuit simulation. It has been implemented in a circuit simulator and is demonstrated for simulation of self-heating in a bipolar low frequency power transistor. The main advantage of this simulation method is that not only the 3-D thermal behavior of the whole chip is simulated, but that this is also directly coupled to the electrical device behavior by means of the power dissipation and temperature distribution in the device. This offers the possibility for the circuit designer to simulate 3-D, coupled, thermal-electrical problems with a circuit simulator. As an example, the influence of the emitter contacting on the internal temperature and current distribution of a BJT is investigate

Cross-layer system reliability assessment framework for hardware faults

System reliability estimation during early design phases facilitates informed decisions for the integration of effective protection mechanisms against different classes of hardware faults. When not all system abstraction layers (technology, circuit, microarchitecture, software) are factored in such an estimation model, the delivered reliability reports must be excessively pessimistic and thus lead to unacceptably expensive, over-designed systems. We propose a scalable, cross-layer methodology and supporting suite of tools for accurate but fast estimations of computing systems reliability. The backbone of the methodology is a component-based Bayesian model, which effectively calculates system reliability based on the masking probabilities of individual hardware and software components considering their complex interactions. Our detailed experimental evaluation for different technologies, microarchitectures, and benchmarks demonstrates that the proposed model delivers very accurate reliability estimations (FIT rates) compared to statistically significant but slow fault injection campaigns at the microarchitecture level.Peer ReviewedPostprint (author's final draft

A survey of carbon nanotube interconnects for energy efficient integrated circuits

This article is a review of the state-of-art carbon nanotube interconnects for Silicon application with respect to the recent literature. Amongst all the research on carbon nanotube interconnects, those discussed here cover 1) challenges with current copper interconnects, 2) process & growth of carbon nanotube interconnects compatible with back-end-of-line integration, and 3) modeling and simulation for circuit-level benchmarking and performance prediction. The focus is on the evolution of carbon nanotube interconnects from the process, theoretical modeling, and experimental characterization to on-chip interconnect applications. We provide an overview of the current advancements on carbon nanotube interconnects and also regarding the prospects for designing energy efficient integrated circuits. Each selected category is presented in an accessible manner aiming to serve as a survey and informative cornerstone on carbon nanotube interconnects relevant to students and scientists belonging to a range of fields from physics, processing to circuit design

Accelerating Electromigration Aging: Fast Failure Detection for Nanometer ICs

For practical testing and detection of electromigration (EM) induced failures in dual damascene copper interconnects, one critical issue is creating stressing conditions to induce the chip to fail exclusively under EM in a very short period of time so that EM sign-off and validation can be carried out efficiently. Existing acceleration techniques, which rely on increasing temperature and current densities beyond the known limits, also accelerate other reliability effects making it very difficult, if not impossible, to test EM in isolation. In this article, we propose novel EM wear-out acceleration techniques to address the aforementioned issue. First we show that multi-segment interconnects with reservoir and sink structures can be exploited to significantly speedup the EM wear-out process. Based on this observation, we propose three strategies to accelerate EM induced failure: reservoir-enhanced acceleration, sink-enhanced acceleration, and a hybrid method that combines both reservoir and sink structures. We then propose several configurable interconnect structures that exploit atomic reservoirs and sinks for accelerated EM testing. Such configurable interconnect structures are very flexible and can be used to achieve significant lifetime reductions at the cost of some routing resources. Using the proposed technique, EM testing can be carried out at nominal current densities, and at a much lower temperature compared to traditional testing methods. This is the most significant contribution of this work since, to our knowledge, this is the only method that allows EM testing to be performed in a controlled environment without the risk of invoking other reliability effects that are also accelerated by elevated temperature and current density. Simulation results show that, using the proposed method, we can reduce the EM lifetime of a chip from 10 years down to a few hours 10^5X acceleration under the 150C temperature limit, which is sufficient for practical EM testing of typical nanometer CMOS ICs

Improved micro-contact resistance model that considers material deformation, electron transport and thin film characteristics

This paper reports on an improved analytic model forpredicting micro-contact resistance needed for designing microelectro-mechanical systems (MEMS) switches. The originalmodel had two primary considerations: 1) contact materialdeformation (i.e. elastic, plastic, or elastic-plastic) and 2) effectivecontact area radius. The model also assumed that individual aspotswere close together and that their interactions weredependent on each other which led to using the single effective aspotcontact area model. This single effective area model wasused to determine specific electron transport regions (i.e. ballistic,quasi-ballistic, or diffusive) by comparing the effective radius andthe mean free path of an electron. Using this model required thatmicro-switch contact materials be deposited, during devicefabrication, with processes ensuring low surface roughness values(i.e. sputtered films). Sputtered thin film electric contacts,however, do not behave like bulk materials and the effects of thinfilm contacts and spreading resistance must be considered. Theimproved micro-contact resistance model accounts for the twoprimary considerations above, as well as, using thin film,sputtered, electric contact