Coverage measurement for software application level verification using symbolic trajectory evaluation techniques

Copyright © 2004 IEEEDesign verification of a systems-on-a-chip is a bottleneck for hardware design projects. A new solution is a design verification methodology that applies coverage driven verification at the embedded software application level. This methodology currently lacks an appropriate coverage measurement technique. This paper proposes a new coverage model for the software application level. Using this coverage model, a novel technique to represent and measure coverage is described. This technique uses ideas such as control graph structures and checking algorithms to estimate the completeness of software application verification.Adriel Cheng, Atanas Parashkevov, Cheng-Chew Li

A REVIEW ON REUSE OF SOFTWARE COMPONENTS FOR SUSTAINABLE SOLUTIONS IN DEVELOPMENT PROCESS

Effective reuse of a software product will increase the productivity, reliability and maintainability. It saves the development and verification time and reduces the risk and the cost involved in the software development. From the literature in this field, it is noticed that very few attempts had been made to identify or measure the software reuse process level.      Also planning for reuse and determining the suitable component for reuse in a system development process have some significant challenges. To overcome these challenges reuse engineers must apply effective methods to identify high potential and quality reusable software components

A REVIEW ON REUSE OF SOFTWARE COMPONENTS FOR SUSTAINABLE SOLUTIONS IN DEVELOPMENT PROCESS

Effective reuse of a software product will increase the productivity, reliability and maintainability. It saves the development and verification time and reduces the risk and the cost involved in the software development. From the literature in this field, it is noticed that very few attempts had been made to identify or measure the software reuse process level.      Also planning for reuse and determining the suitable component for reuse in a system development process have some significant challenges. To overcome these challenges reuse engineers must apply effective methods to identify high potential and quality reusable software components

Accelerating Coverage Closure For Hardware Verification Using Machine Learning

Functional verification is used to confirm that the logic of a design meets its specification. The most commonly used method for verifying complex designs is simulation-based verification. The quality of simulation-based verification is based on the quality and diversity of the tests that are simulated. However, it is time consuming and compute intensive on account of the fact that a large volume of tests must be simulated to exhaustively exercise the design functionality in order to find and fix logic bugs. A common measure of success of this exercise is in the form of a metric known as functional coverage. Coverage is typically indicated as a percentage of functionality covered by the test suite. This thesis proposes a novel methodology to construct a model using SVM, Gradient Boosting Classifier and Neural Networks aimed at replacing random test generation for speeding up coverage collection

Determining Cases of Scenarios to Improve Coverage in Simulation-based Verification

Abstract—Functional verification of complex designs is still dominated by simulation-based approaches. In particular, Coverage-driven Verification (CDV) is well acknowledged and ap-plied in industry. Here, verification gaps in terms of inadequately checked scenarios are addressed and closed by generating and applying dedicated stimuli. In order to ensure a good coverage and, by this, a high verification quality, each scenario is supposed to become sufficiently triggered. However, the considered scenario may be triggered in several fashions and information about that is hardly available in the existing CDV approaches. In this work, we propose an approach which automatically derives this information. Examples and experimental evaluations illustrate how this improves coverage in simulation-based verification. I

Towards Coverage Closure: Using GoldMine Assertions for Generating Design Validation Stimulus

Coordinated Science Laboratory was formerly known as Control Systems Laborator

A Functional Verification Methodology for an Improved Coverage of System-on-Chips

The increasing popularity of System-on-Chip (SoC) circuits results in many new design challenges. One major challenge is to ensure the functional correctness of such complicated circuits. Functional verification is a verification technique used to verify the functional correctness of SoCs. Coverage Directed Test Generation (CDTG) is an essential part of functional verification, where the objective is to generate input stimulus that maximize the coverage of a design. Coverage helps to determine how well the input stimulus verified the design under verification. CDTG techniques analyze coverage results and adapt the input stimulus generation process to improve the coverage. One of the important component of CDTG based tools is the constraint solver. The time efficiency of the verification process depends on the efficiency of the solver. But the constraint solvers associated with CDTG tools require large amount of memory and time to generate input stimuli for SoCs. The solvers cannot generate solutions which are evenly distributed in search space, in order to attain the required coverage. The aim of this thesis is to provide a practical framework that enables the generation of evenly distributed input stimuli. A basic feature of the search space (data set) is that it contains k sub populations or clusters. Partitioning the search space into clusters and generating solutions from the partitions can improve the evenness of the solutions generated by the solver. Hence one of our main contribution is a novel domain partitioning algorithm. The domain partitioning algorithm relies on solution generated by a consistency search algorithm developed for our purpose. The number of partitions (required by the domain partitioning algorithm) is determined by using an algorithm which can find the optimal number of clusters present in a data set. To demonstrate the effectiveness of our approach, we apply our methodology on Constraint Satisfaction Problems (CSPs) and some real life applications

Метод та система верифікації процесорного ядра RISC-V з використанням генератора випадкових інструкцій RISCV-DV від Google

RISC-V має великий потенціал, щоб очолити ринок в сфері вбудованих систем, і на сьогоднішній день вона активно розвивається та впроваджується в наукових колах і промисловості. Розширена перевірка та валідація дуже важливі для того, аби можна було стверджувати, що система відповідає вимогам специфікації щодо функціональних, а також позафункціональних аспектів. Таким чином, в роботі обґрунтовано вибір методу обмеженого генерування тестів в якості базового для використання в створюваному тестовому середовищі верифікації, який дозволяє забезпечити максимальне тестове покриття та мінімальний час симуляції. Запропоновано структурно-функціональну організацію побудови тестового середовища для верифікації процесорного ядра на базі архітектури набору інструкцій з відкритим кодом RISC-V з використанням генератора випадкових інструкцій RISC-DV від Google, що дозволило створити на її основі систему верифікації, яка реалізує зазначений вище метод обмеженого генерування тестів.RISC-V has great potential to lead the market in embedded systems, and today it is actively developing and implementing in academia and industry. Advanced verification and validation are very important in order to be able to state that the system meets the requirements of the specification in terms of functional as well as non-functional aspects. Therefore, in this work the choice of the method of limited test generation as a basic one for use in the created test environment of verification is substantiated, which allows to provide the maximum test coverage and the minimum simulation time. A structural and functional organization of the test environment for verification of the processor core based on the architecture of the open source instruction set RISC-V using random random generator RISC-DV from Google, which allowed to create a verification system that implements the above method of limited generating tests is suggested