Fault Analysis And Test For Bridge Defect In Resistive Random Access Memory

Resistive Random-Access Memory (ReRAM) is one of the potential candidates of emerging semiconductor memory to replace the conventional memory technologies.Besides, ReRAM offers many attractive advantages, such as non-volatile, scalable, low power consumption, and fast data access. Due to the infancy stage of this emerging memory, ReRAM is prone to have bridge defects that could lead to test escape and reliability issues. Moreover, with the lack of electrical model for ReRAM, this research presents an electrical ReRAM model that was designed with SILVACO Electronic Design Automation (EDA) software. All ReRAM elements designed used 22nm Complementary Metal Oxide Semiconductor (CMOS) transistors and a novel non- CMOS device, known as memristor, as the memory cell array. The optimal memristor model that had been proposed by D. Biolek was chosen among three published memristor SPICE models. The selection was made based on the performance analysis.Furthermore, simulation of 2x2 cell ReRAM was executed in order to prove the functionality of the design. The designed ReRAM model functioned as desired based on the simulation results. In addition, the defective behaviors of the faulty ReRAM that were impacted by the three types of bridge defects, (bridge between wordlines; BW, bridge between bitlines; BB and bridge between bitlines and wordlines; BBW) had been studied in this work. The faulty ReRAM model was established by injecting the defects into the designed electrical ReRAM model. As this ReRAM employed a non-CMOS device as its memory cells, the defect that occurred might behave differently than that happens in conventional memories. This could cause the faulty ReRAM to escape from the available memory test. The simulation of the faulty ReRAM model showed that the bridge defects had been due to the Undefined State Faults (USFs) during reading operation. Besides, any faulty in ReRAM caused by USF makes setting the cell to the desired logical value a challenging task, and this fault is difficult to be detected. Hence, a new Design-for-Testability (DfT) technique was proposed to detect these USFs. This technique, known as Adaptive Sensing Read Voltage (ASRV), had been developed based on the mechanism of memristor, as well as the function of sense amplifier. Apart from that, a slight circuit modification was done to implement the DfT circuitry. Based on the simulation results during the DfT implementation, the proposed DfT technique successfully detects the USFs that occurred when 0Ω ≤ RBW ≤ 50Ω for BW injection, 36Ω ≤ RBB ≤ 372Ω for BB injection and 140Ω ≤ RBBW ≤ 210Ω for BBW injection.However, this DfT technique might not suitable for BBW injection as it might kill the healthy cell

A Modern Primer on Processing in Memory

Modern computing systems are overwhelmingly designed to move data to computation. This design choice goes directly against at least three key trends in computing that cause performance, scalability and energy bottlenecks: (1) data access is a key bottleneck as many important applications are increasingly data-intensive, and memory bandwidth and energy do not scale well, (2) energy consumption is a key limiter in almost all computing platforms, especially server and mobile systems, (3) data movement, especially off-chip to on-chip, is very expensive in terms of bandwidth, energy and latency, much more so than computation. These trends are especially severely-felt in the data-intensive server and energy-constrained mobile systems of today. At the same time, conventional memory technology is facing many technology scaling challenges in terms of reliability, energy, and performance. As a result, memory system architects are open to organizing memory in different ways and making it more intelligent, at the expense of higher cost. The emergence of 3D-stacked memory plus logic, the adoption of error correcting codes inside the latest DRAM chips, proliferation of different main memory standards and chips, specialized for different purposes (e.g., graphics, low-power, high bandwidth, low latency), and the necessity of designing new solutions to serious reliability and security issues, such as the RowHammer phenomenon, are an evidence of this trend. This chapter discusses recent research that aims to practically enable computation close to data, an approach we call processing-in-memory (PIM). PIM places computation mechanisms in or near where the data is stored (i.e., inside the memory chips, in the logic layer of 3D-stacked memory, or in the memory controllers), so that data movement between the computation units and memory is reduced or eliminated.Comment: arXiv admin note: substantial text overlap with arXiv:1903.0398

Impact of Temperature-Induced Oxide Defects on HfxZr1−xO2 Ferroelectric Tunnel Junction Memristor Performance

In this work, we evaluate the importance of the postmetallization annealing (PMA) temperature on the performance of HfxZr1−xO2-based ferroelectric tunnel junctions (FTJs). Our results indicate a significant difference in tunneling electroresistance (TER) ratio and endurance, depending on the PMA temperature despite negligible variations in remanent polarization. We conclude that the minimization of conductive oxide defect states is central to achieve high performance. Through carefully optimized PMA conditions, we demonstrate FTJs with a TER = 3 and low mean cycle-to-cycle variation of < 1.5% combined with at least 16 separable conductance states providing a 4-bit resolution analog FTJ

In-Depth X-Ray Photoelectron Spectroscopy of Resistive Switching Devices

This work has explored the possibility of using x-ray photoelectron spectroscopy (XPS), for studying the chemical properties (i.e. atomic ratios and oxidation states) of several metal-insulator-metal (MIM) structures. This thesis aims to better understand the operation mechanism that imposes a reversible change in the resistance state of the studied devices. Three different configurations (ITO/ZTO*/Pt, Pt/ZTO/Ti-Au, ITO/GIO*/Au) were fabricated following a physical vapour deposition methodology and patterned using shadow masks, specifically designed for this purpose. An electrical characterization was performed first, to evaluate the uniformity between the devices through the study of their pristine state and second, to change the resistance state, applying a high voltage signal, followed by an in-depth XPS analysis. The XPS argon cluster depth profiling of the produced MIM structures showed that the resistive switching mechanism of the Pt/ZTO/Ti-Au device was not ionic, since no change of cation ratios and oxidation states were observed throughout the depth of the device, comparing pristine state and the low resistive state (LRS). The ITO/GIO/Au device exhibited area-dependent electroforming, which led to an irreversible change in the forward direction. Remarkably, the diode was free of any hysteresis after electroforming. The XPS depth profile revealed an increased indium concentration within the bulk region near the ITO after electroforming, compared to the pristine state of the device. Hence, despite being irreversible, the resistance change of the device is clearly related to an ionic mechanism. *ZTO: zinc-tin oxide; GIO: gallium-indium oxid

Achieving Reliable and Sustainable Next-Generation Memories

Conventional memory technology scaling has introduced reliability challenges due to dysfunctional, improperly formed cells and crosstalk from increased cell proximity. Furthermore, as the manufacturing effort becomes increasingly complex due to these deeply scaled technologies, holistic sustainability is negatively impacted. The development of new memory technologies can help overcome the capacitor scaling limitations of DRAM. However, these technologies have their own reliability concerns, such as limited write endurance in the case of Phase Change Memories (PCM). Moreover, emerging system requirements, such as in-memory encryption to protect sensitive or private data and operation in harsh environments create additional challenges that must be addressed in the context of reliability and sustainability. This dissertation provides new multifactor and ultimately unified solutions to address many of these concerns in the same system. In particular, my contributions toward mitigating these issues are as follows. I present GreenChip and GreenAsic, which together provide the first tools to holistically evaluate new computer architecture, chip, and memory design concepts for sustainability. These tools provide detailed estimates of manufacturing and operational-phase metrics for different computing workloads and deployment scenarios. Using GreenChip, I examined existing DRAM reliability techniques in the context of their holistic sustainability impact, including my own technique to mitigate bitline crosstalk. For PCM, I provided a new reliability technique with no additional storage overhead that substantially increases the lifetime of an encrypted memory system. To provide bit-level error correction, I developed compact linked-list and Bloom-filter-based bit-level fault map structures, that provide unprecedented levels of error tabulation, combined with my own novel error correction and lifetime extension approaches based on these maps for less area than traditional ECC. In particular, FaME, can correct N faults using N bits when utilizing a bit-level fault map. For operation in harsh environments, I created a triple modular redundancy (TMR) pointer-based fault map, HOTH, which specifically protects cells shown to be weak to radiation. Finally, to combine the analyses of holistic sustainability and memory lifetime, I created the LARS technique, which adjusts the GreenChip indifference analysis to account for the additional sustainability benefit provided by increased reliability and lifetime

Circuit and Architecture Co-Design of STT-RAM for High Performance and Low Energy

Spin-Transfer Torque Random Access Memory (STT-RAM) has been proved a promising emerging nonvolatile memory technology suitable for many applications such as cache mem- ory of CPU. Compared with other conventional memory technology, STT-RAM offers many attractive features such as nonvolatility, fast random access speed and extreme low leakage power. However, STT-RAM is still facing many challenges. First of all, programming STT-RAM is a stochastic process due to random thermal fluctuations, so the write errors are hard to avoid. Secondly, the existing STT-RAM cell designs can be used for only single-port accesses, which limits the memory access bandwidth and constraints the system performance. Finally, while other memory technology supports multi-level cell (MLC) design to boost the storage density, adopting MLC to STT-RAM brings many disadvantages such as requirement for large transistor and low access speed. In this work, we proposed solutions on both circuit and architecture level to address these challenges. For the write error issues, we proposed two probabilistic methods, namely write-verify- rewrite with adaptive period (WRAP) and verify-one-while-writing (VOW), for performance improvement and write failure reduction. For dual-port solution, we propose the design methods to support dual-port accesses for STT-RAM. The area increment by introducing an additional port is reduced by leveraging the shared source-line structure. Detailed analysis on the performance/reliability degrada- tion caused by dual-port accesses is performed, and the corresponding design optimization is provided. To unleash the potential of MLC STT-RAM cache, we proposed a new design through a cross-layer co-optimization. The memory cell structure integrated the reversed stacking of magnetic junction tunneling (MTJ) for a more balanced device and design trade-off. In architecture development, we presented an adaptive mode switching mechanism: based on application’s memory access behavior, the MLC STT-RAM cache can dynamically change between low latency SLC mode and high capacity MLC mode. Finally, we present a 4Kb test chip design which can support different types and sizes of MTJs. A configurable sensing solution is used in the test chip so that it can support wide range of MTJ resistance. Such test chip design can help to evaluate various type of MTJs in the future

A survey of near-data processing architectures for neural networks

Data-intensive workloads and applications, such as machine learning (ML), are fundamentally limited by traditional computing systems based on the von-Neumann architecture. As data movement operations and energy consumption become key bottlenecks in the design of computing systems, the interest in unconventional approaches such as Near-Data Processing (NDP), machine learning, and especially neural network (NN)-based accelerators has grown significantly. Emerging memory technologies, such as ReRAM and 3D-stacked, are promising for efficiently architecting NDP-based accelerators for NN due to their capabilities to work as both high-density/low-energy storage and in/near-memory computation/search engine. In this paper, we present a survey of techniques for designing NDP architectures for NN. By classifying the techniques based on the memory technology employed, we underscore their similarities and differences. Finally, we discuss open challenges and future perspectives that need to be explored in order to improve and extend the adoption of NDP architectures for future computing platforms. This paper will be valuable for computer architects, chip designers, and researchers in the area of machine learning.This work has been supported by the CoCoUnit ERC Advanced Grant of the EU’s Horizon 2020 program (grant No 833057), the Spanish State Research Agency (MCIN/AEI) under grant PID2020-113172RB-I00, and the ICREA Academia program.Peer ReviewedPostprint (published version

Increasing Off-Chip Bandwidth and Mitigating Dark Silicon via Switchable Pins

Off-chip memory bandwidth has been considered as one of the major limiting factors to processor performance, especially for multi-cores and many-cores. Conventional processor design allocates a large portion of off-chip pins to deliver power, leaving a small number of pins for processor signal communication. We observed that the processor requires much less power than that can be supplied during memory intensive stages in some cases. In this work, we propose a dynamic pin switch technique to alleviate the bandwidth limitation issue. The technique is introduced to dynamically exploit the surplus pins for power delivery in the memory intensive phases and uses them to provide extra bandwidth for the program executions, thus significantly boosting the performance. We also explore its performance benefit in the era of Phase-change memory (PCM) and prove that the technique can be applied beyond DRAM-based memory systems. On the other hand, the end of Dennard Scaling has led to a large amount of inactive or significantly under-clocked transistors on modern chip multi-processors in order to comply with the power budget and prevent the processors from overheating. This so-called “dark silicon” is one of the most critical constraints that will hinder the scaling with Moore’s Law in the future. While advanced cooling techniques, such as liquid cooling, can effectively decrease the chip temperature and alleviate the power constraints; the peak performance, determined by the maximum number of transistors which are allowed to switch simultaneously, is still confined by the amount of power pins on the chip package. In this paper, we propose a novel mechanism to power up the dark silicon by dynamically switching a portion of I/O pins to power pins when off-chip communications are less frequent. By enabling extra cores or increasing processor frequency, the proposed strategy can significantly boost performance compared with traditional designs. Using the switchable pins can increase inter-socket bandwidth as one of performance bottlenecks. Multi-socket computer systems are popular in workstations and servers. However, they suffer from the relatively low bandwidth of inter-socket communication especially for massive parallel workloads that generates many inter-socket requests for synchronizations and remote memory accesses. The inter-socket traffic poses a huge pressure on the underlying networks fully connecting all processors with the limited bandwidth that is confined by pin resources. Given the constraint, we propose to dynamically increase the inter-socket band-width, trading off with lower off-chip memory bandwidth when the systems have heavy inter-socket communication but few off-chip memory accesses. The design increases the physical bandwidth of inter-socket communication via switching the function of pins from off-chip memory accesses to inter-socket communication

Fast Transients in Non-Volatile Resistive Memories (RRAM) Using Tantalum Pentoxide as Solid Electrolyte

The semiconductor electronics industry has followed Moore\u27s law austerely since 1965 fueling the microelectronics revolution and major technological advancements. Over the recent decades, the semiconductor industry has proven to be very successful, particularly by scaling the geometry of devices ever smaller. The device scaling has been very effective in boosting productivity yielding astonishing integration levels while simultaneously dramatically dropping the price per bit. However, the future of device scaling remains unclear. It is certain that device scaling will face severe reliability, cost and energy issues in the future. Therefore, there is a need to identify alternative technology platforms. Reconfigurable devices are considered as one of the key alternatives. However, the widespread aggressive acceptance of reconfigurable devices in the semiconductor industry faces many different challenges. One of the major challenges is the size of the switching matrix. One solution to overcome this challenge is to replace the present SRAM (Static Random Access Memory) switch with a non-volatile resistive memory switch. Some of the advantages of these switches are low cost, CMOS compatibility and simple structure. Given such advantages, it is essential to elucidate the working principle as well as the reliability issues. Since these non-volatile resistive switch devices are new to the semiconductor electronics industry, it is crucially important to explore novel structures for improved device architectures and to develop adequate measurement techniques to inspect and characterize these novel resistive switch devices. In this thesis, novel structures of RRAM devices with constricted electrode area close to the size of a single conducting filament of around 10 nm have been explored to improve device performance. Also, new measurement setups have been developed and proprietary test circuits have been designed, built and tested in order to acquire accurate and reliable data to investigate device performance. Some of the notable achievements of the developed measurement setups are measurement capability of switching transient with accuracy of 4 ns, high resistance measurements up to 1.6 GΩ, accurate endurance test within 1 ms/cycle and limiting current during SET to \u3c 20 μA without noticeable overshoot within 500 ps