A generalized software framework for accurate and efficient management of performance goals

A number of techniques have been proposed to provide runtime performance guarantees while minimizing power consumption. One drawback of existing approaches is that they work only on a fixed set of components (or actuators) that must be specified at design time. If new components become available, these management systems must be redesigned and reimplemented. In this paper, we propose PTRADE, a novel performance management framework that is general with respect to the components it manages. PTRADE can be deployed to work on a new system with different components without redesign and reimplementation. PTRADE's generality is demonstrated through the management of performance goals for a variety of benchmarks on two different Linux/x86 systems and a simulated 128-core system, each with different components governing power and performance tradeoffs. Our experimental results show that PTRADE provides generality while meeting performance goals with low error and close to optimal power consumption.United States. Defense Advanced Research Projects Agency. The Ubiquitous High Performance Computing Progra

Microarchitecture optimization for timing and layout

In recent years the drive to produce more complex integrated circuits while spending less design time has driven the demand for design automation tools. The search for design automation methods has resulted in the design of numerous behavioral synthesis and logic synthesis tools. This report describes a system that fills the gap between traditional behavioral synthesis and logic synthesis tools. Techniques are introduced for improving the microarchitecture structure and using feedback from lower-level optimization tools to guide design optimizations while attempting to meet user specified area and time constraints. These techniques include the capability for mixing layout styles such as custom layout for random-logic components and bit-slicing for regularly structured components. In this manner the entire design, control logic and datapath, can be optimized at the same time. Further, this paper presents a new methodology for microarchitecture-level optimization that greatly reduces the amount of technology-specific knowledge necessary to perform the optimizations

Implementing an Integrated Signaling and Power Distribution Control System for Remotely Located Devices

A system was designed and implemented that combined the distribution of high-current power with a digital control signal over a common conductor. Two different versions of this system were implemented. Initially, a design based on of commercially available parts was created and tested to prove that the concept of combining communications and power is valid. The resulting design was then miniaturized to show that the system might be combined onto a single integrated circuit. In the miniaturization process, some circuit blocks were redesigned to take advantage of the flexibility provided by ASIC designs. Both the proof of concept and the VLSI implementations were completely designed, implemented, and fully tested. It was shown that the system can be miniaturized. The miniaturization provided the advantages of smaller overall implementation size and higher reliability due to decreased part count. The disadvantage of the miniaturization process was that the design became fixed once it was fabricated in silicon

Development of limb volume measuring system

The mechanisms underlying the reductions in orthostatic tolerance associated with weightlessness are not well established. Contradictory results from measurements of leg volume changes suggest that altered venomotor tone and reduced blood flow may not be the only contributors to orthostatic intolerance. It is felt that a more accurate limb volume system which is insensitive to environmental factors will aid in better quantification of the hemodynamics of the leg. Of the varous limb volume techniques presently available, the ultrasonic limb volume system has proven to be the best choice. The system as described herein is free from environmental effects, safe, simple to operate and causes negligible radio frequency interference problems. The segmental ultrasonic ultrasonic plethysmograph is expected to provide a better measurement of limb volume change since it is based on cross-sectional area measurements

Development of a static feed water electrolysis system

A one person level oxygen generation subsystem was developed and production of the one person oxygen metabolic requirements, 0.82 kg, per day was demonstrated without the need for condenser/separators or electrolyte pumps. During 650 hours of shakedown, design verification, and endurance testing, cell voltages averaged 1.62 V at 206 mA/sq cm and at average operating temperature as low as 326 K, virtually corresponding to the state of the art performance previously established for single cells. This high efficiency and low waste heat generation prevented maintenance of the 339 K design temperature without supplemental heating. Improved water electrolysis cell frames were designed, new injection molds were fabricated, and a series of frames was molded. A modified three fluid pressure controller was developed and a static feed water electrolysis that requires no electrolyte in the static feed compartment was developed and successfully evaluated

Petri net approaches for modeling, controlling, and validating flexible manufacturing systems

In this dissertation, we introduce the fundamental ideas and constructs of Petri net models such as ordinary, timed, colored, stochastic, control, and neural, and present some studies that emphasize Petri nets theories and applications as extended research fields that provide suitable platforms in modeling, controlling, validating, and evaluating concurrent systems, information systems, and a versatile dynamic system and manufacturing systems;We then suggest some of extensions that help make Petri nets useful for modeling and analyzing discrete event systems and manufacturing systems models based on the context of a versatile manufacturing system, and applies extended Petri nets models to several manufacturing systems such as an assembly cell, an Automated Palletized Conveyor System, and a tooling machine to show increased modeling power and efficient analysis methods;Finally, Validation methods are presented for these models and results of a performance analysis from a deterministic and stochastic model are used to reorganize and re-evaluate a manufacturing system in order to increase its flexibility

General purpose simulator system study

Modifications to computerized simulator system for space shuttle and space station application

An integrated SDN-based architecture for Passive Optical Networks

Passive Optical Network (PON) are often managed by non-flexible, proprietary network management systems. Software Defined Networking (SDN) opens the way for a more efficient operation and management of networks. We describe a new SDN-based architecture for Ethernet Passive Optical Networks (EPON), in which some functions of the Optical Line Terminal (OLT) are virtualized and located in an external controller, while keeping the rest of the PON functionality around an Open Flow switch. This opens the way for an improved management of the resource usage, bandwidth allocation, Quality-of-Service (QoS) monitoring and enforcement, or power consumption management, among other possibilities. In order to maintain the time-sensitive nature of the EPON operations, synchronous ports are added to the switch. OpenFlow messages are extended in order to cope with the PON-related parameters. Results based on simulations demonstrate that our proposal performs similarly or better than legacy architectures, in terms of delay and throughput.Postprint (author's final draft

클럭 게이팅 및 플립 플롭 동시 최적화를 위한 설계 및 알고리즘

학위논문 (석사)-- 서울대학교 대학원 : 공과대학 전기·정보공학부, 2019. 2. 김태환.본 논문에서는 표준 셀에서부터 배치 단계에 이르는 다양한 설계단에에서 칩의 동적 전력을 최적화 기법을 소개한다. 이 연구는 우선 데이터 구동형 (즉, 토글링 기반) 클럭 게이팅이 종래 클럭 게이팅 기법들에서 결코 다루어지지 않았던 플립 플 롭의 합성과 밀접하게 통합될 수 있는 방법을 연구한다. 우리의 관측의 핵심은 플립 플롭 셀의 일부 내부 부품이 클럭 게이팅 인에이블 신호를 생성 하기 위해 재사용 될 수 있다는 것이다. 이를 바탕으로 eXOR-FF 라고 불리는 새롭게 최적화된 플립 플롭 배선 구조를 제안합니다. 이 구조에서는 매 클럭 주기마다 내부 로직을 재사용 하여 클럭 게이팅을 통해 플립 플롭을 활성화할지 또는 비활성화할지 결정합니다. 모든 쌍의 플립 플롭 및 토글릴 감지 로직에서의 영역을 절약함에 따라서 누설 및 동적 전력의 절전 효과를 달성합니다. 그런 다음, 두 가지고유한 장점을 제공하는 배치/타이밍 인식 클럭 게이팅 탐색에 대한 포괄적인 방법론을 제안합니다. 해당 방 법론은 eXOR-FF 의 이점을 극대화하고, 전력 소비 및 타이밍 영향의 분해에 대한 정밀 분석을 수행하고 틀럭 게이팅 참색의 핵심 엔진을 비용기능으로 변환하는데 가장 적합합니다. ISCAS89, ITC89, ITC99 및 IWLS 2005의 벤치 마크 회로를 사용 한 실험을 통해 제안 된 방법이 이전의 데이터 구동 클록 게이팅 방식과 비교하여 총 전력을 5.6 % 및 면적으로 5.3 % 줄일 수 있음을 보여 주었다.In this paper, we introduce dynamic power optimization techniques applicable for various design stage from standard cell to placement stage. This work firstly investi�gates the problem of how designing data-driven (i.e., toggling based) clock gating can be closely integrated with the synthesis of flip-flops, which has never been addressed in the prior clock gating works. Our key observation is that some internal part of a flip-flop cell can be reused to generate its clock gating enable signal. Based on this, we propose a newly optimized flip-flop wiring structure, called eXOR-FF, in which an internal logic can be reused for every clock cycle to decide if the flip-flop is to be activated or inactivated through clock gating, thereby achieving area saving (thus, leakage as well as dynamic power saving) on every pair of flip-flop and its toggling detection logic. Then, we propose a comprehensive methodology of placement/timing�aware clock gating exploration that provides two unique strengths: best suited for max�imally exploiting the benefit of eXOR-FFs and precise analyses on the decomposition of power consumptions and timing impact, and translating them into cost functions in core engine of clock gating exploration. Through experiments with benchmark circuits in ISCAS89, ITC89, ITC99 and IWLS 2005, it is shown that our proposed method is able to reduce the total power by 5.6% and total cell area by 5.3% compared with the previous data-driven clock gating method in [1].Abstract Contents List of Tables List of Figures 1 Introduction 1.1 Power Consumption in CMOS Digital Design 1.2 Low Power Design Methodologies 1.3 Contribution of This Thesis 2 Preliminary and Motivations 6 2.1 Background 2.2 Observation on Area and Power Saving 2.3 Observation on Timing Impact 3 Redesign of Flip-flops Specialized for Clock Gating 3.1 Observation on Area Impact 4 Placement-aware Clock Gating Methodology Utilizing eXOR-FF Cells 4.1 Overall Design Flow 4.2 Cost Formulation for Conventional Clock Gating 4.3 Cost Formulation for Our Clock Gating using eXOR-FFs 5 Experiments 5.1 Experimental Setup 5.2 Experimental Results 5.3 Comparing with Industry Algorithm 6 Conclusion Abstract (In Korean)Maste