Continuous-time Algorithms and Analog Integrated Circuits for Solving Partial Differential Equations

Analog computing (AC) was the predominant form of computing up to the end of World War II. The invention of digital computers (DCs) followed by developments in transistors and thereafter integrated circuits (IC), has led to exponential growth in DCs over the last few decades, making ACs a largely forgotten concept. However, as described by the impending slow-down of Moore’s law, the performance of DCs is no longer improving exponentially, as DCs are approaching clock speed, power dissipation, and transistor density limits. This research explores the possibility of employing AC concepts, albeit using modern IC technologies at radio frequency (RF) bandwidths, to obtain additional performance from existing IC platforms. Combining analog circuits with modern digital processors to perform arithmetic operations would make the computation potentially faster and more energy-efficient. Two AC techniques are explored for computing the approximate solutions of linear and nonlinear partial differential equations (PDEs), and they were verified by designing ACs for solving Maxwell\u27s and wave equations. The designs were simulated in Cadence Spectre for different boundary conditions. The accuracies of the ACs were compared with finite-deference time-domain (FDTD) reference techniques. The objective of this dissertation is to design software-defined ACs with complementary digital logic to perform approximate computations at speeds that are several orders of magnitude greater than competing methods. ACs trade accuracy of the computation for reduced power and increased throughput. Recent examples of ACs are accurate but have less than 25 kHz of analog bandwidth (Fcompute) for continuous-time (CT) operations. In this dissertation, a special-purpose AC, which has Fcompute = 30 MHz (an equivalent update rate of 625 MHz) at a power consumption of 200 mW, is presented. The proposed AC employes 180 nm CMOS technology and evaluates the approximate CT solution of the 1-D wave equation in space and time. The AC is 100x, 26x, 2.8x faster when compared to the MATLAB- and C-based FDTD solvers running on a computer, and systolic digital implementation of FDTD on a Xilinx RF-SoC ZCU1275 at 900 mW (x15 improvement in power-normalized performance compared to RF-SoC), respectively

Solving differential equations in analog domain

A growth in the use of analog computers has been seen in the last few years despite of the dominance of digital computers, this is due to the fact that it was noticed that analog computers could solve differential equations not only faster but also in a more efficient way, which means drawing less power. This lead to the interest in studying how a computer can solve this type of equations and what it takes to do so. With this in mind a circuit that describes a variation of the law of exponential decay is proposed, this implicated the design of an folded cascode operational amplifier, which was implemented using 130nm MOS technology. This then led to the study of this amplifier in an integrator configuration as well as the proposed circuit, which in a later stage was made configurable by adding a logic controller to control the resistors that establish the coefficients of the equation. With the obtained results it was possible to validate the objective specifications for the amplifier as well as observe that the circuit was able to come to successful results within the known constraints of the components used for this circuit. This circuit was able to reach solutions much faster than a digital computer facing the same problem, 30s versus 0.3s, while consuming considerably less power, 40mW versus 72W.Nos últimos anos tem se verificado um aumento no uso de computadores analógicos apesar do contínuo domínio por parte dos computadores digitais, isto deve-se principalmente ao facto de que foi observado que os computadores analógicos conseguem não só resolver equações diferenciais muito mais rápidos, mas também que estes conseguem fazê-lo de uma maneira muito mais eficiente, ou seja, gastando menos potência. Isto levou ao interesse em estudar como estes computadores resolvem estas equações e também o que é necessário para o fazer. Devido as estes fatores, um circuito que representa uma variante da lei de decaimento exponencial foi proposto para ser resolvido, isto implicou o dimensionamento de um amplificador operacional de topologia "folded-cascode", que foi implementado usando tecnologia MOS de 130nm. Isto levou ao estudo deste amplificador na sua montagem integradora para além do circuito proposto, por fim este circuito foi tornado configurável por meio de um controlador lógico adicional a controlar as resistências que determinam os valores dos coeficientes desta equação. Com os resultados obtidos, foi não só possível validar que as características definidas para o amplificador foram cumpridas como também observar que o circuito conseguiu obter resultados bem sucedidos dentro das limitações dos componentes do circuito. Assim este circuito conseguiu chegar ao resultado destas equações num tempo muito inferior ao de um computador digital, 30s contra 0.3s, enquanto consumia uma potência estimada consideravelmente mais baixa, 40mW contra 72W

Measurements, Models, Systems and Design

531 s.