Electron Beam Testing of Integrated Circuits Using a Picosecond Photoelectron Scanning Electron Microscope

A scanning electron microscope which uses an ultrashort pulsed laser / photocathode combination as an electron source produces electron pulses of about 1 ps in duration at a 100 MHz repetition rate. By using this instrument in the stroboscopic voltage contrast mode we have performed waveform measurements at the internal nodes of high speed silicon integrated circuits at room and at liquid nitrogen temperature, and studied the propagation of ultrafast electrical transients on various interconnection structures

Design, simulation and fabrication of a mems in-situ contactless sensor to detect plasma induced damage during reactive ion etching

The present trend in the semiconductor industry is towards submicron devices. An inevitable process technique in achieving this is by reactive ion etching of the polysilicon gate. During RIE, the gate oxide may get damaged due to several causes. One of the main causes of the damage is the non-uniformity of the plasma. It is reported that these plasma inconsistencies are mainly due to electrode design and that they create spatial plasma potential fluctuation. These fluctuations are reported to be in the range of 10-20 Volts. By providing an in-situ monitoring of the wafers, the reliability of the device could be established. The purpose of this sensor is to detect the spatial fluctuations. It works on the principle of electrostatic forces. It is made of polysilicon (gate material) and consists of two cantilevers separated by 2μm constituting a parallel plate capacitor configuration. The design, simulation and fabrication of the sensor was carried out. The test results demonstrated that sensors with beam lengths 150μm, 200μm and 250μm deflect by 2μm at externally applied voltages of 65, 56, and 50 volts respectively. Optimized beam dimensions that would deflect by 1.2µm at an applied voltage of 20 Volts is estimated from the experimental results and has the following dimensions: length of the cantilever = 200μm, width = 2μm, the thickness = 1.6μm, and the space between the cantilevers is = 1.2μm

Hybrid Diagnosis Model To Determine Fault Isolation For Scan Chain Failure Analysis On 22nm Fabrication Process

With the rapid growth of Very Large Scale Integration (VLSI) in complex designs, there is high demand for Design for Testability (DFT). Vast study has proven that Scan based testing is achieving good test coverage with lower cost and smaller die area and is widely used in the industry. Scan chain fault diagnosis plays an important role as with the implementation of Scan based testing, it is reported that 10%-30% of defects in a Scan based design occurs within the Scan chain itself. Currently, there are three main types of stand-alone diagnosis models available, which are: software-based diagnosis, tester-based diagnosis and hardware-based diagnosis, where each has its disadvantages and limitations. In this project, the author proposed a hybrid Scan chain failure analysis technique that uses the proposed software-based diagnosis to obtain a list of possible failing suspect Scan cells, followed by the proposed tester-based diagnosis to further isolate the fault to a single failing device suspect. This proposed hybrid diagnosis algorithm ensures that Scan chain faults such as stuck-at and transition faults can be root-caused with lesser time and low complexity for both solid and marginal failures. Four case studies were successfully carried out to evaluate the proposed hybrid diagnosis algorithm on a 22nm fabrication process technology Device under Test (DUT) System-on-Chip (SOC) product, where the fault isolation was able to isolate a single failing device suspect for all four case studies, indicating a 100% fault isolation success rate

RON-BEAM DEBUG AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS

A current research project at IMAG/TIM3 Laboratory aims at an integrated test system combining the use of the Scanning Electron Microscope (SEM), used in voltage contrast mode, with a new high-level approach of fault location in complex VLSI circuits, in order to reach a complete automated diagnosis process. Two research themes are induced by this project, which are: prototype validation of known circuits, on which CAD information is available, and failure analysis of unknown circuits, which are compared to reference circuits. For prototype validation, a knowledge-based approach to fault location is used. Concerning failure analysis, automatic image comparison based on pattern recog- nition techniques is performed. The purpose of the paper is to present these two methodologies, focusing on the SEM-based data acquisition process

Design of Hardware with Quantifiable Security against Reverse Engineering

Semiconductors are a 412 billion dollar industry and integrated circuits take on important roles in human life, from everyday use in smart-devices to critical applications like healthcare and aviation. Saving today\u27s hardware systems from attackers can be a huge concern considering the budget spent on designing these chips and the sensitive information they may contain. In particular, after fabrication, the chip can be subject to a malicious reverse engineer that tries to invasively figure out the function of the chip or other sensitive data. Subsequent to an attack, a system can be subject to cloning, counterfeiting, or IP theft. This dissertation addresses some issues concerning the security of hardware systems in such scenarios. First, the issue of privacy risks from approximate computing is investigated in Chapter 2. Simulation experiments show that the erroneous outputs produced on each chip instance can reveal the identity of the chip that performed the computation, which jeopardizes user privacy. The next two chapters deal with camouflaging, which is a technique to prevent reverse engineering from extracting circuit information from the layout. Chapter 3 provides a design automation method to protect camouflaged circuits against an adversary with prior knowledge about the circuit\u27s viable functions. Chapter 4 provides a method to reverse engineer camouflaged circuits. The proposed reverse engineering formulation uses Boolean Satisfiability (SAT) solving in a way that incorporates laser fault injection and laser voltage probing capabilities to figure out the function of an aggressively camouflaged circuit with unknown gate functions and connections. Chapter 5 addresses the challenge of secure key storage in hardware by proposing a new key storage method that applies threshold-defined behavior of memory cells to store secret information in a way that achieves a high degree of protection against invasive reverse engineering. This approach requires foundry support to encode the secrets as threshold voltage offsets in transistors. In Chapter 6, a secret key storage approach is introduced that does not rely on a trusted foundry. This approach only relies on the foundry to fabricate the hardware infrastructure for key generation but not to encode the secret key. The key is programmed by the IP integrator or the user after fabrication via directed accelerated aging of transistors. Additionally, this chapter presents the design of a working hardware prototype on PCB that demonstrates this scheme. Finally, chapter 7 concludes the dissertation and summarizes possible future research