Automated Synthesis of SEU Tolerant Architectures from OO Descriptions

SEU faults are a well-known problem in aerospace environment but recently their relevance grew up also at ground level in commodity applications coupled, in this frame, with strong economic constraints in terms of costs reduction. On the other hand, latest hardware description languages and synthesis tools allow reducing the boundary between software and hardware domains making the high-level descriptions of hardware components very similar to software programs. Moving from these considerations, the present paper analyses the possibility of reusing Software Implemented Hardware Fault Tolerance (SIHFT) techniques, typically exploited in micro-processor based systems, to design SEU tolerant architectures. The main characteristics of SIHFT techniques have been examined as well as how they have to be modified to be compatible with the synthesis flow. A complete environment is provided to automate the design instrumentation using the proposed techniques, and to perform fault injection experiments both at behavioural and gate level. Preliminary results presented in this paper show the effectiveness of the approach in terms of reliability improvement and reduced design effort

On-going and future research at the Sulcis site in Sardinia, Italy. Characterization and experimentation at a possible future CCS pilot

National Italian funding has recently been allocated for the construction of a 350 MWe coal-fired power plant / CCS demonstration plant in the Sulcis area of SW Sardinia, Italy. In addition, the recently approved EC-funded ENOS project (ENabling Onshore CO2 Storage in Europe) will use the Sulcis site as one of its main field research laboratories. Site characterization is already ongoing, and work has begun to design gas injection experiments at 100-200 m depth in a fault. This article gives an overview of results to date and plans for the future from the Sapienza University of Rome research group

Innovative Techniques for Testing and Diagnosing SoCs

We rely upon the continued functioning of many electronic devices for our everyday welfare, usually embedding integrated circuits that are becoming even cheaper and smaller with improved features. Nowadays, microelectronics can integrate a working computer with CPU, memories, and even GPUs on a single die, namely System-On-Chip (SoC). SoCs are also employed on automotive safety-critical applications, but need to be tested thoroughly to comply with reliability standards, in particular the ISO26262 functional safety for road vehicles. The goal of this PhD. thesis is to improve SoC reliability by proposing innovative techniques for testing and diagnosing its internal modules: CPUs, memories, peripherals, and GPUs. The proposed approaches in the sequence appearing in this thesis are described as follows: 1. Embedded Memory Diagnosis: Memories are dense and complex circuits which are susceptible to design and manufacturing errors. Hence, it is important to understand the fault occurrence in the memory array. In practice, the logical and physical array representation differs due to an optimized design which adds enhancements to the device, namely scrambling. This part proposes an accurate memory diagnosis by showing the efforts of a software tool able to analyze test results, unscramble the memory array, map failing syndromes to cell locations, elaborate cumulative analysis, and elaborate a final fault model hypothesis. Several SRAM memory failing syndromes were analyzed as case studies gathered on an industrial automotive 32-bit SoC developed by STMicroelectronics. The tool displayed defects virtually, and results were confirmed by real photos taken from a microscope. 2. Functional Test Pattern Generation: The key for a successful test is the pattern applied to the device. They can be structural or functional; the former usually benefits from embedded test modules targeting manufacturing errors and is only effective before shipping the component to the client. The latter, on the other hand, can be applied during mission minimally impacting on performance but is penalized due to high generation time. However, functional test patterns may benefit for having different goals in functional mission mode. Part III of this PhD thesis proposes three different functional test pattern generation methods for CPU cores embedded in SoCs, targeting different test purposes, described as follows: a. Functional Stress Patterns: Are suitable for optimizing functional stress during I Operational-life Tests and Burn-in Screening for an optimal device reliability characterization b. Functional Power Hungry Patterns: Are suitable for determining functional peak power for strictly limiting the power of structural patterns during manufacturing tests, thus reducing premature device over-kill while delivering high test coverage c. Software-Based Self-Test Patterns: Combines the potentiality of structural patterns with functional ones, allowing its execution periodically during mission. In addition, an external hardware communicating with a devised SBST was proposed. It helps increasing in 3% the fault coverage by testing critical Hardly Functionally Testable Faults not covered by conventional SBST patterns. An automatic functional test pattern generation exploiting an evolutionary algorithm maximizing metrics related to stress, power, and fault coverage was employed in the above-mentioned approaches to quickly generate the desired patterns. The approaches were evaluated on two industrial cases developed by STMicroelectronics; 8051-based and a 32-bit Power Architecture SoCs. Results show that generation time was reduced upto 75% in comparison to older methodologies while increasing significantly the desired metrics. 3. Fault Injection in GPGPU: Fault injection mechanisms in semiconductor devices are suitable for generating structural patterns, testing and activating mitigation techniques, and validating robust hardware and software applications. GPGPUs are known for fast parallel computation used in high performance computing and advanced driver assistance where reliability is the key point. Moreover, GPGPU manufacturers do not provide design description code due to content secrecy. Therefore, commercial fault injectors using the GPGPU model is unfeasible, making radiation tests the only resource available, but are costly. In the last part of this thesis, we propose a software implemented fault injector able to inject bit-flip in memory elements of a real GPGPU. It exploits a software debugger tool and combines the C-CUDA grammar to wisely determine fault spots and apply bit-flip operations in program variables. The goal is to validate robust parallel algorithms by studying fault propagation or activating redundancy mechanisms they possibly embed. The effectiveness of the tool was evaluated on two robust applications: redundant parallel matrix multiplication and floating point Fast Fourier Transform

Modeling fluid flow in fault zones: two different-scale cases from Majella Mountain and East Pacific Rise

A quantitative assessment of how rock discontinuities (i.e., fractures and faults) control the migration of geofluids is critical in several areas of geological and environmental sciences. In this project I concentrated my attention to two problems at the extreme range of the spectrum of fluids properties, in two different geological settings: the flow of CO2 from a natural reservoir and the melt migration in mid-ocean transform fracture zones. The specific targets of my studies were: -a fault zone exposed in the Roman Valley Quarry (Lettomanoppello, Italy); -the fracture zone of the Siqueiros Transform Fault (East Pacific Rise); The thesis is structured starting from a general overview of the two study cases and then describing in detail the methods used and the results achieved for each scenario. To model the migration of CO2 in a fault zone, I created a new pipeline that starts from the field data and then uses open source software and new developed codes to model the fluid flow in a fault zone considering all its components: core and damage zones. I selected the Roman Valley Quarry as study site because of the great exposure of the inner structure of two oblique slip normal faults. Besides, the massive presence of fluid migration in the form of tar in the fracture systems makes this site a good natural analogue for studies of fluid flow in fractured media. The work on the fault zone of Roman Valley Quarry can be divided in three main parts: 1. Collection of quantitative information on the fractures/fault distribution; 2. Application of state-of-art modelling techniques to infer the hydraulic properties of the fractured reservoir from field data; 3. Numerical modeling of flow of CO2 in the fractured reservoir; I modeled the data collected in the field to infer the hydraulic properties of the fractured reservoir (i.e. the Bolognano Formation). I employed a hybrid numerical technique, modeling the damage zones as a fractured medium and the core as a continuum medium. This allowed me to: 1. characterize the hydraulic differences observed in the field between the southern part and the northern part of the fault; 2. characterize the hydraulic parameters of the footwall and hangingwall damage zones; 3. use these values to model the fluid flow in the whole fault zone, coupling damage zones and core. I built Discrete Fracture Networks (DFN) models using both commercial (Move®) and open source software (dfnWorks, developed by Los Alamos National Laboratory). Move® has been used to model the hydraulic differences found in the field between the northern and southern sector of the fault. dfnWorks has been used to infer the hydraulic parameters of the fracture systems of the damage zones of the fault. These parameters have then been used to upscale the properties of the fractures to an equivalent continuum medium, in order to simulate the fluid flow in the entire fault zone, coupling the core and the damage zones. The numerical model of CO2 flow in the fault zone was developed using the open source software PFLOTRAN. To better reproduce a real-life case study, I simulated the injection of CO2 into the footwall of the Roman Valley Quarry fault. Hydrostatic initial conditions have been imposed, according to the pressure distribution in the domain. An injection mass rate has been imposed at the location of the well to simulate the injection of CO2. First, I run a number of simulations to test the workflow and verify the consistency of the numerical results. Once I obtained a stable numerical framework, I run several numerical experiments. Results from numerical experiments show that the distribution of the CO2 in the domain appears mainly controlled by the permeability distribution in the damage zone of the fault. The CO2 in fact accumulates in the high permeability fault footwall, where the injection happens and reaches the maximum values of the pressure and saturation close to the core of the fault, that is characterized by a low permeability. Although developed and calibrated for the specific site of the Roman Valley Quarry fault, the methodology developed in this study can be extended to different geological contests. Although not originally part of my PhD proposal, the involvement on the Off-Axis Seamounts Investigations at Siqueiros (OASIS) project was a unique opportunity to learn how to collect, process and employ geophysical data to characterize and model fluid flow (in this case, magmatic melts) near a fault zone. The OASIS (Off-Axis Seamount Investigations at Siqueiros) expedition is a multidisciplinary effort to systematically investigate the 8˚20’N Seamount Chain to better understand the melting and transport processes in the southern portion of the 9˚-10˚N segment of the East Pacific Rise (EPR). The 8˚20’N Seamount Chain extends ~160 km west from its initiation, ~15km northwest of the EPR-Siqueiros ridge transform intersection (RTI). To investigate the emplacement of the 8˚20’N Seamounts, shipboard EM-122 multibeam, BGM-3 gravity, and towed magnetometer data were collected using the R/V Atlantis in November 2016. Multibeam data show that the seamount chain is characterized by the emplacement of discrete seamounts in the distal portion of the chain, while east of 105˚20’ W, the chain is a nearly-continuous volcanic ridge comprised of small cones and coalesced edifices with some evidence for rift zones, craters and calderas on the larger constructs. Isostatic anomalies, calculated along several profiles crossing the main edifices of the seamount chain, indicate that the seamounts formed within 100 km of the EPR ridge axis. Excess crustal thickness variations of 0.5 to 1 km, derived from the Residual Mantle Bouguer Anomaly, suggest an increase in melt flux eastward along the chain. Consistently high emplacement volumes are observed east of -105 ˚20’ W, ~130 km from the ridge axis corresponding with lithosphere younger than 2 Myr. Inverted three-dimensional magnetization data indicate that the seamounts have recorded a series of magnetic reversals along the chain, which correlate to reversals recorded in the surrounding seafloor upon which the seamounts were built. However, reversals along the eastern portion of the chain appear skewed to the west indicating that seamount formation is likely long-lived. The geophysical observations indicate that the overall seamount chain is age progressive, and suggest a coeval volcanism in a region 15-100km from the EPR. The seamounts do not follow absolute plate motions, but are located consistently 15-20 km north of the Siqueiros fracture zone, which further suggests that their formation is linked to the location and tectonic evolution of the Siqueiros-EPR ridge-transform intersection. These findings have implications for the location/origin of the melt region feeding the EPR as well as how melt is transported near a fracture zone. In fact, the seamounts chain does not follow an hotspot reference frame, but instead runs parallel to the fracture zone, at a constant distance. This observation is unusual, compared to the other seamounts in the region. Evidences of plate direction rotation in variation of the main trend of the chain can be observed. They can be attributed to events of plate rotations that characterized the evolution of the Siqueiros Transform Fault as according to Pockanly et al., (1997): the seamount chain may have formed with the first event of plate reorganization from 3.5 Ma, with the inset of the volcanism close to the RTI. We could think about a melt migration model that takes into account the tectonic evolution of the area, pointing out the role of a stress concentration in the vicinity of the RTI as triggering mechanism for the volcanism

Magmatic Subsidence of the East Pacific Rise (EPR) at 18˚14\u27S Revealed Through Fault Restoration of Ridge Crest Bathymetry

The fault restoration technique of De Chabalier and Avouac [1994] is applied to an ultra-highresolution bathymetry data set from the East Pacific Rise (EPR) at 18140S. Fault offsets are calculated and subtracted from the original seafloor bathymetry to examine the morphology of the unfaulted seafloor surface within an area encompassing the ridge axis 400 [1] 1600 m in dimension. The restored topography reveals a gently sloping seafloor 200 m wide, which slopes 5 inward toward the spreading axis. We attribute this inward sloping seafloor to subsidence within the axial trough due to subsurface magmatic deflation. The vertical deformation field extracted from the bathymetry is used to characterize the ridge axis fault population present in the area. Median fault throws (9 m for inward-facing and 8 m for outwardfacing faults) are comparable to values measured for nearby mature abyssal hill fault populations, suggesting a genetic link. However, median fault spacings (70 and 46 m) are an order of magnitude smaller, and estimated total extensional strain is 3[1]–4[1] greater than values measured for ridge flank faults. These differences indicate the axial fault population at 18140S cannot be rafted onto the ridge flanks to form abyssal hill faults without significant modification, presumably via volcanic burial. We attribute the dense faulting observed in this area to slip on axial fissures during subsidence of the crestal region. The surface subsidence of a volcanic edifice can be modeled in terms of volume change in the magma source reservoir and volume of magma withdrawn from the reservoir. Using the relationship derived for a sill-like magma body, we estimate that the axial depression at 18140S could represent magma withdrawal associated with a small number (4–22) of the frequent dike injection and eruption events required to build the upper crust during the evolution of the trough. The subsidence volumes represented by the axial topography at 18140S are a small percentage of the underlying upper crustal sections (3–4%), suggesting that only a minor mismatch between magma recharge and withdrawal from the axial melt lens during ongoing plate separation could account for this pronounced axial depression

Exploiting the IEEE 1149.1 Standard for Software Reliability Evaluation in Space Applications

The IEEE 1149.1 standard (boundary-scan) was originally developed as a technology to provide in-circuit testing of digital devices. Its effectiveness lead to unanticipated successes such as its extension to support on-line monitoring and in-circuit emulation. Meanwhile, its applicability for fault-injection had already been demonstrated by academic prototypes. In this paper we describe the first commercial tool, the BSCAN4FI plug in for Xception®, that provides support for software reliability evaluation for aeronautics and space applications using the boundary-scan technology as a means for controlled fault-injection. This tool allows transparent integration testing without any modification to the original system to be deployed and was developed specifically for the SPARC V.7 TSC695f space processor. Besides extended fault models and test features only made possible through this technology, in-system non-intrusive monitoring capabilities are also made possible.info:eu-repo/semantics/publishedVersio

DeSyRe: on-Demand System Reliability

The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As fabrication technology scales down, chips are becoming less reliable, thereby incurring increased power and performance costs for fault tolerance. To make matters worse, power density is becoming a significant limiting factor in SoC design, in general. In the face of such changes in the technological landscape, current solutions for fault tolerance are expected to introduce excessive overheads in future systems. Moreover, attempting to design and manufacture a totally defect and fault-free system, would impact heavily, even prohibitively, the design, manufacturing, and testing costs, as well as the system performance and power consumption. In this context, DeSyRe delivers a new generation of systems that are reliable by design at well-balanced power, performance, and design costs. In our attempt to reduce the overheads of fault-tolerance, only a small fraction of the chip is built to be fault-free. This fault-free part is then employed to manage the remaining fault-prone resources of the SoC. The DeSyRe framework is applied to two medical systems with high safety requirements (measured using the IEC 61508 functional safety standard) and tight power and performance constraints

Ultra-thin clay layers facilitate seismic slip in carbonate faults

Many earthquakes propagate up to the Earth's surface producing surface ruptures. Seismic slip propagation is facilitated by along-fault low dynamic frictional resistance, which is controlled by a number of physico-chemical lubrication mechanisms. In particular, rotary shear experiments conducted at seismic slip rates (1 ms(-1)) show that phyllosilicates can facilitate co-seismic slip along faults during earthquakes. This evidence is crucial for hazard assessment along oceanic subduction zones, where pelagic clays participate in seismic slip propagation. Conversely, the reason why, in continental domains, co-seismic slip along faults can propagate up to the Earth's surface is still poorly understood. We document the occurrence of micrometer-thick phyllosilicate-bearing layers along a carbonate-hosted seismogenic extensional fault in the central Apennines, Italy. Using friction experiments, we demonstrate that, at seismic slip rates (1 ms(-1)), similar calcite gouges with pre-existing phyllosilicate-bearing (clay content ≤3 wt.%) micro-layers weaken faster than calcite gouges or mixed calcite-phyllosilicate gouges. We thus propose that, within calcite gouge, ultra-low clay content (≤3 wt.%) localized along micrometer-thick layers can facilitate seismic slip propagation during earthquakes in continental domains, possibly enhancing surface displacement

Anti-Tamper Method for Field Programmable Gate Arrays Through Dynamic Reconfiguration and Decoy Circuits

As Field Programmable Gate Arrays (FPGAs) become more widely used, security concerns have been raised regarding FPGA use for cryptographic, sensitive, or proprietary data. Storing or implementing proprietary code and designs on FPGAs could result in the compromise of sensitive information if the FPGA device was physically relinquished or remotely accessible to adversaries seeking to obtain the information. Although multiple defensive measures have been implemented (and overcome), the possibility exists to create a secure design through the implementation of polymorphic Dynamically Reconfigurable FPGA (DRFPGA) circuits. Using polymorphic DRFPGAs removes the static attributes from their design; thus, substantially increasing the difficulty of successful adversarial reverse-engineering attacks. A variety of dynamically reconfigurable methodologies exist for implementation that challenge designers in the reconfigurable technology field. A Hardware Description Language (HDL) DRFPGA model is presented for use in security applications. The Very High Speed Integrated Circuit HDL (VHSIC) language was chosen to take advantage of its capabilities, which are well suited to the current research. Additionally, algorithms that explicitly support granular autonomous reconfiguration have been developed and implemented on the DRFPGA as a means of protecting its designs. Documented testing validates the reconfiguration results and compares power usage, timing, and area estimates from a conventional and DRFPGA model