Electrocardiogram (ECG/EKG) using FPGA

FPGAs (Field Programmable Gate Arrays) are finding wide acceptance in medical systems for their ability for rapid prototyping of a concept that requires hardware/software co-design, for performing custom processing in parallel at high data rates and be programmed in the field after manufacturing. Based on the market demand, the FPGA design can be changed and no new hardware needs to be purchased as was the case with ASICs (Application Specific Integrated Circuit) and CPLDs (Complex Programmable Logic Device). Medical companies can now move over to FPGAs saving cost and delivering highly-efficient upgradable systems. ECG (Electrocardiogram) is considered to be a must have feature for a medical diagnostic imaging system. This project attempts at implementing ECG heart-rate computation in an FPGA. This project gave me exposure to hardware engineering, learning about the low level chips like Atmel UC3A3256 micro-controller on an Atmel EVK1105 board which is used as a simulator for generating the ECG signal, the operational amplifiers for amplifying and level-shifting the ECG signal, the A/D converter chip for analog to digital conversion of the ECG signal, the internal workings of FPGA, how different hardware components communicate with each other on the system and finally some signal processing to calculate the heart rate value from the ECG signal

Matrix-free multigrid block-preconditioners for higher order Discontinuous Galerkin discretisations

Efficient and suitably preconditioned iterative solvers for elliptic partial differential equations (PDEs) of the convection-diffusion type are used in all fields of science and engineering. To achieve optimal performance, solvers have to exhibit high arithmetic intensity and need to exploit every form of parallelism available in modern manycore CPUs. The computationally most expensive components of the solver are the repeated applications of the linear operator and the preconditioner. For discretisations based on higher-order Discontinuous Galerkin methods, sum-factorisation results in a dramatic reduction of the computational complexity of the operator application while, at the same time, the matrix-free implementation can run at a significant fraction of the theoretical peak floating point performance. Multigrid methods for high order methods often rely on block-smoothers to reduce high-frequency error components within one grid cell. Traditionally, this requires the assembly and expensive dense matrix solve in each grid cell, which counteracts any improvements achieved in the fast matrix-free operator application. To overcome this issue, we present a new matrix-free implementation of block-smoothers. Inverting the block matrices iteratively avoids storage and factorisation of the matrix and makes it is possible to harness the full power of the CPU. We implemented a hybrid multigrid algorithm with matrix-free block-smoothers in the high order DG space combined with a low order coarse grid correction using algebraic multigrid where only low order components are explicitly assembled. The effectiveness of this approach is demonstrated by solving a set of representative elliptic PDEs of increasing complexity, including a convection dominated problem and the stationary SPE10 benchmark.Comment: 28 pages, 10 figures, 10 tables; accepted for publication in Journal of Computational Physic

AsterixDB: A Scalable, Open Source BDMS

AsterixDB is a new, full-function BDMS (Big Data Management System) with a feature set that distinguishes it from other platforms in today's open source Big Data ecosystem. Its features make it well-suited to applications like web data warehousing, social data storage and analysis, and other use cases related to Big Data. AsterixDB has a flexible NoSQL style data model; a query language that supports a wide range of queries; a scalable runtime; partitioned, LSM-based data storage and indexing (including B+-tree, R-tree, and text indexes); support for external as well as natively stored data; a rich set of built-in types; support for fuzzy, spatial, and temporal types and queries; a built-in notion of data feeds for ingestion of data; and transaction support akin to that of a NoSQL store. Development of AsterixDB began in 2009 and led to a mid-2013 initial open source release. This paper is the first complete description of the resulting open source AsterixDB system. Covered herein are the system's data model, its query language, and its software architecture. Also included are a summary of the current status of the project and a first glimpse into how AsterixDB performs when compared to alternative technologies, including a parallel relational DBMS, a popular NoSQL store, and a popular Hadoop-based SQL data analytics platform, for things that both technologies can do. Also included is a brief description of some initial trials that the system has undergone and the lessons learned (and plans laid) based on those early "customer" engagements

Microelectronic cmos implementation of a machine learning technique for sensor calibration

An integrated machine-learning based adaptive circuit for sensor calibration implemented in standard 0.18μm CMOS technology with 1.8V power supply is presented in this paper. In addition to linearizing the device response, the proposed system is also capable to correct offset and gain errors. The building blocks conforming the adaptive system are designed and experimentally characterized to generate numerical high-level models which are used to verify the proper performance of each analog block within a defined multilayer perceptron architecture. The network weights, obtained from the learning phase, are stored in a microcontroller EEPROM memory, and then loaded into each of the registers of the proposed integrated prototype. In order to verify the proposed system performance, the non-linear characteristic of a thermistor is compensated as an application example, achieving a relative error er below 3% within an input span of 130°C, which is almost 6 times less than the uncorrected response. The power consumption of the whole system is 1.4mW and it has an active area of 0.86mm 2 . The digital programmability of the network weights provides flexibility when a sensor change is required

Improved memory loading techniques for the TSRV display system

A recent upgrade of the TSRV research flight system at NASA Langley Research Center retained the original monochrome display system. However, the display memory loading equipment was replaced requiring design and development of new methods of performing this task. This paper describes the new techniques developed to load memory in the display system. An outdated paper tape method for loading the BOOTSTRAP control program was replaced by EPROM storage of the characters contained on the tape. Rather than move a tape past an optical reader, a counter was implemented which steps sequentially through EPROM addresses and presents the same data to the loader circuitry. A cumbersome cassette tape method for loading the applications software was replaced with a floppy disk method using a microprocessor terminal installed as part of the upgrade. The cassette memory image was transferred to disk and a specific software loader was written for the terminal which duplicates the function of the cassette loader

Thin Flexible Radio Frequency Identification Tags And Subsystems Thereof

Embodiments according to the present invention comprised RFID tags comprised of components disposed on a flexible conformal substrate. The substrate may be substantially transparent or opaque and the components may be comprised of organic electronic components. Components and circuits may be manufactured using thin-film deposition processes or by deposition of metal-containing inks using inkjet technology. Exemplary use of an embodiment according to the present invention is as a component in an on-vehicle radio-frequency (RF) automated toll system.Georgia Tech Research Corporatio

Custom architectures for fuzzy and neural networks controllers

Standard hardware, dedicated microcontroller or application specific circuits can implement fuzzy logic or neural network controllers. This paper presents efficient architecture approaches to develop controllers using specific circuits. A generator uses several tools that allow translating the initial problem specification to a specific circuit implementation, by using HDL descriptions. These HDL description files can be synthesized to get the FPGA configuration bit-stream.Facultad de Informátic