On-board B-ISDN fast packet switching architectures. Phase 2: Development. Proof-of-concept architecture definition report

For the next-generation packet switched communications satellite system with onboard processing and spot-beam operation, a reliable onboard fast packet switch is essential to route packets from different uplink beams to different downlink beams. The rapid emergence of point-to-point services such as video distribution, and the large demand for video conference, distributed data processing, and network management makes the multicast function essential to a fast packet switch (FPS). The satellite's inherent broadcast features gives the satellite network an advantage over the terrestrial network in providing multicast services. This report evaluates alternate multicast FPS architectures for onboard baseband switching applications and selects a candidate for subsequent breadboard development. Architecture evaluation and selection will be based on the study performed in phase 1, 'Onboard B-ISDN Fast Packet Switching Architectures', and other switch architectures which have become commercially available as large scale integration (LSI) devices

Experimental Evaluation of an ATM Host Interface

We have previously reported a design for a host interface board intended to connect workstations to ATM networks, and an implementation that was underway. Since then, we have made some modifications to the hardware implementation, and implemented software support. Our prototype connects an IBM RS/6000 to a SONET-based ATM network carrying data at the OC-3c rate of 155Mbps. In this paper, we discuss an experimental evaluation of the interface and supporting software. Our experiments uncovered an unexpected bottleneck in providing high bandwidth to application processes, and we suggest a number of possible improvements to workstation architectures to address this bottleneck

Performance Evaluation of Specialized Hardware for Fast Global Operations on Distributed Memory Multicomputers

Workstation cluster multicomputers are increasingly being applied for solving scientific problems that require massive computing power. Parallel Virtual Machine (PVM) is a popular message-passing model used to program these clusters. One of the major performance limiting factors for cluster multicomputers is their inefficiency in performing parallel program operations involving collective communications. These operations include synchronization, global reduction, broadcast/multicast operations and orderly access to shared global variables. Hall has demonstrated that a .secondary network with wide tree topology and centralized coordination processors (COP) could improve the performance of global operations on a variety of distributed architectures [Hall94a]. My hypothesis was that the efficiency of many PVM applications on workstation clusters could be significantly improved by utilizing a COP system for collective communication operations. To test my hypothesis, I interfaced COP system with PVM. The interface software includes a virtual memory-mapped secondary network interface driver, and a function library which allows to use COP system in place of PVM function calls in application programs. My implementation makes it possible to easily port any existing PVM applications to perform fast global operations using the COP system. To evaluate the performance improvements of using a COP system, I measured cost of various PVM global functions, derived the cost of equivalent COP library global functions, and compared the results. To analyze the cost of global operations on overall execution time of applications, I instrumented a complex molecular dynamics PVM application and performed measurements. The measurements were performed for a sample cluster size of 5 and for message sizes up to 16 kilobytes. The comparison of PVM and COP system global operation performance clearly demonstrates that the COP system can speed up a variety of global operations involving small-to-medium sized messages by factors of 5-25. Analysis of the example application for a sample cluster size of 5 show that speedup provided by my global function libraries and the COP system reduces overall execution time for this and similar applications by above 1.5 times. Additionally, the performance improvement seen by applications increases as the cluster size increases, thus providing a scalable solution for performing global operations

Advanced information processing system: The Army fault tolerant architecture conceptual study. Volume 2: Army fault tolerant architecture design and analysis

Described here is the Army Fault Tolerant Architecture (AFTA) hardware architecture and components and the operating system. The architectural and operational theory of the AFTA Fault Tolerant Data Bus is discussed. The test and maintenance strategy developed for use in fielded AFTA installations is presented. An approach to be used in reducing the probability of AFTA failure due to common mode faults is described. Analytical models for AFTA performance, reliability, availability, life cycle cost, weight, power, and volume are developed. An approach is presented for using VHSIC Hardware Description Language (VHDL) to describe and design AFTA's developmental hardware. A plan is described for verifying and validating key AFTA concepts during the Dem/Val phase. Analytical models and partial mission requirements are used to generate AFTA configurations for the TF/TA/NOE and Ground Vehicle missions

Software-based adaptive and concurrent self-testing in programmable network interfaces

Emerging network technologies have complex network interfaces that have renewed concerns about network reliability. In this paper, we present an effective low-overhead failure detection technique, which is based on a software watchdog timer that detects network processor hangs and a self-testing scheme that detects interface failures other than processor hangs. The proposed adaptive and concurrent self-testing scheme achieves failure detection by periodically directing the control flow to go through only active software modules in order to detect errors that affect instructions in the local memory of the network interface. The paper shows how this technique can be made to minimize the performance impact on the host system and be completely transparent to the user

Distributed Failure Restoration for Asynchronous Transfer Mode (ATM) Tactical Communication Networks

Asynchronous Transfer Mode (A TM) is an attractive choice for future military communication systems because it can provide high throughput and support multi-service applications. Furthermore its use is consistent with the 'off the shelf technology policy that is currently operated by the Defence Engineering Research Agency of Great Britain. However, A TM has been developed as a civil standard and is designed to operate in network infrastructures with very low failure rates. In contrast, tactical networks are much less reliable. Indeed tactical networks operate on the premise that failures, particularly node failures, are expected. Hence, efficient, automatic failure restoration schemes are essential if an A TM based tactical network is to remain operational. The main objective of this research is the proposal and verification of one or more new restoration algorithms that meet the specific requirements of tactical networks. The aspects of ATM networks that influence restoration algorithms' implementation are discussed. In particular, the features of A TM networks such as the concept of Virtual Paths Virtual Channels and OAM (Operation And Maintenance) mechanisms that facilitate implementation of efficient restoration techniques. The unique characteristics of tactical networks and their impact on restoration are also presented. A significant part of the research was the study and evaluation of existing approaches to failure restoration in civil networks. A critical analysis of the suitability of these approaches to the tactical environment shows no one restoration algorithm fully meets the requirements of tactical networks. Consequently, two restoration algorithms for tactical A TM networks, DRA-TN (Dynamic Restoration Algorithm for Tactical Networks) and PPR-TN (Pre-planned Restoration Algorithm for Tactical Networks), are proposed and described in detail. Since the primary concern of restoration in tactical networks is the recovery of high priority connections the proposed algorithms attempt to restore high-priority connections by disrupting low-priority calls. Also, a number of additional mechanisms are proposed to reduce the use of bandwidth, which is a scarce resource in tactical networks. It is next argued that software simulation is the most appropriate method to prove the consistency of the proposed algorithms, assess their performance and test them on different network topologies as well as traffic and failure conditions. For this reason a simulation software package was designed and built specifically to model the proposed restoration algorithms. The design of the package is presented in detail and the most important implementation issues are discussed. The proposed restoration algorithms are modelled on three network topologies under various traffic loads, and their performance compared against the performance of known algorithms proposed for civil networks. It is shown that DRA-TN and PPR-TN provide better restoration of higher priority traffic. Furthermore, as the traffic load increases the relative performance of the DRA-TN and PPR-TN algorithms increases. The DRA-TN and PPR-TN algorithms are also compared and their advantages and disadvantages noted. Also, recommendations are given about the applicability of the proposed algorithms, and some practical implementation issues are discussed. The number of problems that need further study are briefly described.Defence Engineering Research Agency of Great Britai

Using embedded hardware monitor cores in critical computer systems

The integration of FPGA devices in many different architectures and services makes monitoring and real time detection of errors an important concern in FPGA system design. A monitor is a tool, or a set of tools, that facilitate analytic measurements in observing a given system. The goal of these observations is usually the performance analysis and optimisation, or the surveillance of the system. However, System-on-Chip (SoC) based designs leave few points to attach external tools such as logic analysers. Thus, an embedded error detection core that allows observation of critical system nodes (such as processor cores and buses) should enforce the operation of the FPGA-based system, in order to prevent system failures. The core should not interfere with system performance and must ensure timely detection of errors. This thesis is an investigation onto how a robust hardware-monitoring module can be efficiently integrated in a target PCI board (with FPGA-based application processing features) which is part of a critical computing system. [Continues.

Proceedings of the NSSDC Conference on Mass Storage Systems and Technologies for Space and Earth Science Applications

The proceedings of the National Space Science Data Center Conference on Mass Storage Systems and Technologies for Space and Earth Science Applications held July 23 through 25, 1991 at the NASA/Goddard Space Flight Center are presented. The program includes a keynote address, invited technical papers, and selected technical presentations to provide a broad forum for the discussion of a number of important issues in the field of mass storage systems. Topics include magnetic disk and tape technologies, optical disk and tape, software storage and file management systems, and experiences with the use of a large, distributed storage system. The technical presentations describe integrated mass storage systems that are expected to be available commercially. Also included is a series of presentations from Federal Government organizations and research institutions covering their mass storage requirements for the 1990's