FinFET Cell Library Design and Characterization

abstract: Modern-day integrated circuits are very capable, often containing more than a billion transistors. For example, the Intel Ivy Bridge 4C chip has about 1.2 billion transistors on a 160 mm2 die. Designing such complex circuits requires automation. Therefore, these designs are made with the help of computer aided design (CAD) tools. A major part of this custom design flow for application specific integrated circuits (ASIC) is the design of standard cell libraries. Standard cell libraries are a collection of primitives from which the automatic place and route (APR) tools can choose a collection of cells and implement the design that is being put together. To operate efficiently, the CAD tools require multiple views of each cell in the standard cell library. This data is obtained by characterizing the standard cell libraries and compiling the results in formats that the tools can easily understand and utilize. My thesis focusses on the design and characterization of one such standard cell library in the ASAP7 7 nm predictive design kit (PDK). The complete design flow, starting from the choice of the cell architecture, design of the cell layouts and the various decisions made in that process to obtain optimum results, to the characterization of those cells using the Liberate tool provided by Cadence design systems Inc., is discussed in this thesis. The end results of the characterized library are used in the APR of a few open source register-transfer logic (RTL) projects and the efficiency of the library is demonstrated.Dissertation/ThesisMasters Thesis Computer Engineering 201

3D-printing techniques in a medical setting : a systematic literature review

Background: Three-dimensional (3D) printing has numerous applications and has gained much interest in the medical world. The constantly improving quality of 3D-printing applications has contributed to their increased use on patients. This paper summarizes the literature on surgical 3D-printing applications used on patients, with a focus on reported clinical and economic outcomes. Methods: Three major literature databases were screened for case series (more than three cases described in the same study) and trials of surgical applications of 3D printing in humans. Results: 227 surgical papers were analyzed and summarized using an evidence table. The papers described the use of 3D printing for surgical guides, anatomical models, and custom implants. 3D printing is used in multiple surgical domains, such as orthopedics, maxillofacial surgery, cranial surgery, and spinal surgery. In general, the advantages of 3D-printed parts are said to include reduced surgical time, improved medical outcome, and decreased radiation exposure. The costs of printing and additional scans generally increase the overall cost of the procedure. Conclusion: 3D printing is well integrated in surgical practice and research. Applications vary from anatomical models mainly intended for surgical planning to surgical guides and implants. Our research suggests that there are several advantages to 3D- printed applications, but that further research is needed to determine whether the increased intervention costs can be balanced with the observable advantages of this new technology. There is a need for a formal cost-effectiveness analysis

XNOR Neural Engine: a Hardware Accelerator IP for 21.6 fJ/op Binary Neural Network Inference

Binary Neural Networks (BNNs) are promising to deliver accuracy comparable to conventional deep neural networks at a fraction of the cost in terms of memory and energy. In this paper, we introduce the XNOR Neural Engine (XNE), a fully digital configurable hardware accelerator IP for BNNs, integrated within a microcontroller unit (MCU) equipped with an autonomous I/O subsystem and hybrid SRAM / standard cell memory. The XNE is able to fully compute convolutional and dense layers in autonomy or in cooperation with the core in the MCU to realize more complex behaviors. We show post-synthesis results in 65nm and 22nm technology for the XNE IP and post-layout results in 22nm for the full MCU indicating that this system can drop the energy cost per binary operation to 21.6fJ per operation at 0.4V, and at the same time is flexible and performant enough to execute state-of-the-art BNN topologies such as ResNet-34 in less than 2.2mJ per frame at 8.9 fps.Comment: 11 pages, 8 figures, 2 tables, 3 listings. Accepted for presentation at CODES'18 and for publication in IEEE Transactions on Computer-Aided Design of Circuits and Systems (TCAD) as part of the ESWEEK-TCAD special issu

Computer integrated manufacturing in the chemical industry: Theory & practice

This paper addresses the possibilities of implementing Computer Integrated Manufacturing in the process industry, and the chemical industry in particular. After presenting some distinct differences of the process industry in relation to discrete manufacturing, a number of focal points are discussed. They identify the adaptations to be made to a conventional CIM system, so that it will be applicable to the process industry. Interviews with managers of six chemical firms indicate that the process industry may benefit from a new CIM approach to management thinking.Chemical Industry;Manufacturing;CIM;production

Symbolic analysis tools-the state of the art

This paper reviews the main last generation symbolic analyzers, comparing them in terms of functionality, pointing out also their shortcomings. The state of the art in this field is also studied, pointing out directions for future research

Yield Model Characterization For Analog Integrated Circuit Using Pareto-Optimal Surface

A novel technique is proposed in this paper that achieves a yield optimized design from a set of optimal performance points on the Pareto front. Trade-offs among performance functions are explored through multi-objective optimization and Monte Carlo simulation is used to find the design point producing the best overall yield. One advantage of the approach presented is a reduction in the computational cost normally associated with Monte Carlo simulation. The technique offers a yield optimized robust circuit design solution with transistor level accuracy. An example using an OTA is presented to demonstrate the effectiveness of the work